Datasheet
Table Of Contents
- Title Page - SLWS106H
- IMPORTANT NOTICE
- Contents
- List of Illustrations
- 1 Introduction
- 2 Specifications
- 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)†
- 2.2 Recommended Operating Conditions
- 2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Slave Mode, XTI/ MCLK = 256fs, fs = 48 kHz ( unless otherwise stated)
- 2.4 Digital-Interface Timing
- 3 How to Use the TLV320AIC23B
- Appendix A: Mechanical Data
3−8
LRCIN/
BCLK
DIN/
n n−1 01 n−1n
1/fs
Left Channel Right Channel
1 0 n
MSB LSB
LRCOUT
DOUT
Figure 3−6. Left-Justified Mode Timing
3.3.1.3 I
2
S Mode
In I
2
S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or LRCOUT
(see Figure 3-7).
LRCIN/
BCLK
DIN/
n n−1 01 n−1n
1/fs
Left Channel Right Channel
1 0
MSB LSB
1BCLK
LRCOUT
DOUT
Figure 3−7. I
2
S Mode Timing
3.3.1.4 DSP Mode
The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN and LRCOUT must be connected to the Frame
Sync signal of the McBSP. A falling edge on LRCIN or LRCOUT starts the data transfer. The left-channel data consists
of the first data word, which is immediately followed by the right channel data word (see Figure 3-8). Input word length
is defined by the IWL register. Figure 3−8 shows LRP = 1 (default LRP = 0).
LRCIN/
BCLK
DIN/
n n−1 01 n−1n
Left Channel Right Channel
1 0
MSB LSB MSB LSB
LRCOUT
DOUT
Figure 3−8. DSP Mode Timing