Datasheet

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TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 4 Bit Summary (continued)
RESET
BIT NAME FUNCTION
VALUE
Divider values of M, N, and P to be used in junction with the FSDIV bit for calculation of FS frequency
according to the formula: FS = MCLK / (16 x M x N x P) where: M = 1, 2, .., 128
Determined by D6-D0 with FSDIV = 1
D7-D0 = 10000000 M = 128
D7-D0 = 10000001 M = 1
D7-D0 = 11111111 M = 127
N = 1, 2,.., 16
Determined by D6-D3 with FSDIV = 0, D6-D0 M, N, P
D6-D0 MNP —
D7-D0 = 00000xxx N = 16
D7-D0 = 00001xxx N = 1
D7-D0 = 01111xxx N = 15
P = 1, 2,.., 8
Determined by D2-D0 with FSDIV = 0
D7-D0 = 0xxxx000 P = 8
D7-D0 = 0xxxx001 P = 1
D7-D0 = 0xxxx111 P = 7
Control Register 5A
(1)
D7 D6 D5 D4 D3 D2 D1 D0
0 0 ADPGA
R/W R/W R/W R/W R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
Table 5. A/D PGA Gain
D5 D4 D3 D2 D1 D0 ADPGA
0 1 1 1 1 1 ADC input PGA gain = MUTE
0 1 1 1 1 0 ADC input PGA gain = 54 dB
0 1 1 1 0 1 ADC input PGA gain = 48 dB
0 1 1 1 0 0 ADC input PGA gain = 42 dB
0 1 1 0 1 1 ADC input PGA gain = 40.5 dB
0 1 1 0 1 0 ADC input PGA gain = 39 dB
0 1 1 0 0 1 ADC input PGA gain = 37.5 dB
0 1 1 0 0 0 ADC input PGA gain = 36 dB
0 1 0 1 1 1 ADC input PGA gain = 34.5 dB
0 1 0 1 1 0 ADC input PGA gain = 33 dB
0 1 0 1 0 1 ADC input PGA gain = 31.5 dB
0 1 0 1 0 0 ADC input PGA gain = 30 dB
0 1 0 0 1 1 ADC input PGA gain = 28.5 dB
0 1 0 0 1 0 ADC input PGA gain = 27 dB
0 1 0 0 0 1 ADC input PGA gain = 25.5 dB
0 1 0 0 0 0 ADC input PGA gain = 24 dB
0 0 1 1 1 1 ADC input PGA gain = 22.5 dB
0 0 1 1 1 0 ADC input PGA gain = 21 dB
0 0 1 1 0 1 ADC input PGA gain = 19.5 dB
0 0 1 1 0 0 ADC input PGA gain = 18 dB
0 0 1 0 1 1 ADC input PGA gain = 16.5 dB
0 0 1 0 1 0 ADC input PGA gain = 15 dB
0 0 1 0 0 1 ADC input PGA gain = 13.5 dB
0 0 1 0 0 0 ADC input PGA gain = 12 dB
0 0 0 1 1 1 ADC input PGA gain = 10.5 dB
0 0 0 1 1 0 ADC input PGA gain = 9 dB
0 0 0 1 0 1 ADC input PGA gain = 7.5 dB
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