Datasheet

www.ti.com
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Control Register 3C
(1)
D7 D6 D5 D4 D3 D2 D1 D0
10 Reserved ICID OSR
R/W R/W/S R/W
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 3C Bit Summary
RESET
BIT NAME FUNCTION
VALUE
D5 Reserved 0
Chip ID. These two bits represent the device version number.
ICID = 000 Version 1
ICID = 001 Version 2
ICID = 010 Version 3
D4-D2 ICID 000 ICID = 011 Version 4
ICID = 100 Version 5
ICID = 101 Version 6
ICID = 110 Version 7
ICID = 111 Version 8
OSR option D1-D0 = X1 OSR for DAC Channel is 512 (Max FS = 8 Ksps)
D1-D0 OSR option 00 D1-D0 = 10 OSR for DAC Channel is 256 (Max FS = 16 Ksps)
D1-D0 = 00 OSR for DAC Channel is 128 (Max FS = 26 Ksps)
Control Register 3D
(1)
D7 D6 D5 D4 D3 D2 D1 D0
11 LCDAC
R/W R/W/S
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 3D Bit Summary
RESET
BIT NAME FUNCTION
VALUE
D5-D0 LCDAC
(1)
000000 LCD DAC. These bits represent the input value for the 6-bit LCD DAC.
(1) NOTE: See the Electrical Characteristics table for LCD DAC specification.
Control Register 4
(1)
D7 D6 D5 D4 D3 D2 D1 D0
FSDIV MNP
R/W R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S R/W/S
(1) NOTE: R = Read, W = Write, S = Shadowed
Control Register 4 Bit Summary
RESET
BIT NAME FUNCTION
VALUE
Frame sync division factor FSDIV = 0
D7 FSDIV 0 To write value of P to bits D2-D0 and value of N to bits D6-D3 FSDIV = 1
To write value of M to bits D6-D0
40