Datasheet

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I
2
C Write Sequence
SCL
SDA
A5 A4 A3 A2
A1
A0 0
ACK
B7 B6 B5 B4 B3 R2 R1 R0
I2C
6
A6
I2C
5
I2C
4
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK ACK
Programmable 12C Device Address
Set by Control Register 2
Start Bit = 0
SMARTDM Device
Address
(see Table 3-1)
00000 = Default
11111 = Broadcast Mode
Index Register Address
(Index)
Control Register Data for Write
(Index)
Control Register Data for Write
(Index+1)
SCL
SDA
A5 A4 A3 A2
A1
A0 0
ACK
B7 B6 B5 B4 B3 R2 R1 R0
I2C
6
A6 ACK
I2C
5
I2C
4
SCL
SDA
A5 A4 A3 A2
A1
A0
1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
I2C
6
A6
I2C
5
I2C
4
D7 D6 D5 D4 D3 D2 D1 D0
ACK ACK
Start Bit = 0
Programmable 1 C Device Address
2
Set by Control Register 2
SMARTDM Device Address
(see Table 1)
Index Register Address
(Index)
Stop Bit = 1
xxxxx = Don't Care
Start Bit = 0
Programmable 1 C Device Address
2
Set by Control Register 2
SMARTDM Device Address
(see Table 1)
Control Register Data
(Index)
Control Register Data
(Index+1)
I C Read Sequence
2
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
I
2
C
• Each I
2
C read-from or write-to each codec control register is given by an index register address.
• Read/write sequence always starts with the first byte as I
2
C address followed by 0. During the second byte,
default/broadcast mode is set and the index register address is initialized. For write operation control register,
data to be written is given from the third byte onwards. For read operation, stop-start is performed after the
second byte. Now the first byte is I
2
C address followed by 1. From the second byte onwards, control register
data appears.
• Each time read/write is performed, the index register address is incrimented so that the next read/write is
performed on the next control register.
• During the first write cycle and all write cycles in the broadcast, only the device with address 0000 issues
ACK to the I
2
C.
• Similarly, for a register with multiple sub-registers the sub-register index automatically increments with each
read/write. For example, the first read/write to register 3 read/writes to register 3A, the next to register 3B
and so forth until the last sub-register is reached. At this time the sub-register index wraps back around to
the first sub-register
Figure 31. I
2
C Write Sequence
Figure 32. I
2
C Read Sequence
Each codec has an index register address. To perform a write operation, make the LSB of the first byte as 0
(write) (see Figure 33 ). During the second byte, the index register address is initialized and mode
(broadcast/default) is set. From the third byte onwards, write data to the control register (given by index register)
and increment the index register until stop or repeated start occurs. For operation, make the LSB of the first byte
as 1 (read). From the second byte onwards, AIC starts transmitting data from the control register (given by the
index register) and increments the index register. For setting the index register perform operation the same as
write case for 2 bytes, and then give a stop or repeated start.
36