Datasheet

www.ti.com
DIN/DOUT
(16 Bit)
MSB LSB
D15 D14 D15 D14
0 1 30 3129
D1
FS
32 SCLKs
D1 D0
MSB LSB
D0
Master (CH 1) Slave (CH 2)
SCLK
(Output)
FSD
Master
Master FS
DIN/DOUT
AIC20-1 FSD,
AIC20-2 FS
Slave0
Slave6 Slave4 Slave2 Slave0Slave5 Slave3 Slave1 Slave6 Slave4Slave5Master
AIC20-1 AIC20-2 AIC20-3 AIC20-4
16 Bits
AIC20-2 FSD,
AIC20-3 FS
AIC20-3 FSD,
AIC20-4 FS
Programming Mode
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
For validating the conversion data from this operation:
• For DAC: The DSP needs to give the same data for n1 samples. CH1 picks one of the n1 samples.
• For ADC: CH1 gives the same data for the n1 samples. DSP should pick one of the n1 samples.
Figure 21. Timing Diagram for FSD Output
Figure 22. NOTE: AIC2x #4 FSD should be pulled high.
In the programming mode, the FS signal starts the input/output data stream. Each period of FS contains two
frames as shown in Figures 3-10 and 3-11: data frame and control frame. The data frame contains data
transmitted from the ADC or to the DAC. The control frame contains data to program each codec control register.
The SMARTDM automatically sets the number of time slots per frame equal to the number of codec channels in
the interface. Each time slot contains 16-bit data. The SCLK is used to perform data transfer for the serial
interface between the AIC2x codecs and the DSP. The frequency of SCLK varies, depending on the selected
mode of serial interface. In the stand alone-mode, there are 64 SCLKs (or four time slots) per sampling period. In
the master-slave cascade mode, the number of SLCKs equals 32x(number of codec channels in the cascade).
The digital output data from the ADC is taken from DOUT. The digital input data for the DAC is applied to DIN.
The synchronization clock for the serial communication data and the frame-sync is taken from SCLK. The
frame-sync signal that starts the ADC and DAC data transfer interval is taken from FS. The SMARTDM also
provides a turbo operation, in which the FS's frequency is always the device's sampling frequency, but SCLK is
running at a much higher speed. Thus, there are more than 64 SCLKs for each AIC2x per sampling period, in
which the data frame and control frame occupy only the first 64 SCLKs from the falling edge of the frame-sync
FS.
29