Datasheet

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MCLK
DIN
DOUT
M/SFSD
TLV320AIC20
1
FS
SCLK
3.3 V
MCLK
DIN
DOUT
M/SFSD
TLV320AIC20
2
FS
SCLK
MCLK
DIN
DOUT
M/SFSD
TLV320AIC20
3
FS
SCLK
MCLK
DIN
DOUT
M/SFSD
TLV320AIC20
4
FS
SCLK
IOVDD
CLKOUT
DR
DX
FSX
FSR
CLKX
CLKR
TMS320C5X
TMS320C6X
To CLKOUT
or External Oscillator
Stand-Alone Slave
Asynchronous Sampling (Codecs in cascade are sampled at different sampling frequency)
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 20. Cascade Connection (to DSP Interface)
In the stand-alone slave connection, the FS and SCLK inputs must be synchronized to each other and
programmed according to Section 3.1 (Operating Frequencies). The FS and SCLK input are not required to
synchronize to the MCLK input but must remain active at all times to assure continuous sampling in the data
converter. FSD must be connected to LOW for stand-alone-slave. FS is output for initial 132 MCLK and it is kept
low. The host processor needs to keep the FS pin in high impedence state during this period to avoid contention.
The AIC2x SMARTDM supports different sampling frequencies between the different channels in cascade,
connecting to a single serial port in which all codecs are sampled at the same frequency of FS.
For example: FS1 and FS2 are the desired sampling rates for CH1 and CH2 respectively:
1. FS = MCLK / (16 x M x N x P)
2. FS = n1 x FS1 (n1 = 1, 2, . . ., 8 defined in the control register 3A of CH1)
3. FS = n2 x FS2 (n2 = 1, 2, . . ., 8 defined in the control register 3A of CH2)
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