Datasheet

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SDA
SCL
t
f
t
LOW
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;STA
t
SU;STO
t
BUF
t
r
t
HD;STA
t
f
t
SU;DAT
t
r
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Figure 3. I
2
C / S
2
C Timing Diagram
PARAMETER SYMBOL MIN MAX UNIT
SCL clock frequency t
SCL
0 900 kHz
Hold time (repeated START condition. After this period, the first clock pulse is t
HD;STA
100
generated.
Low period of the SCL clock t
LOW
560
High period of the SCL clock t
HIGH
560
Set-up time for a repeated START condition t
SU;STA
100
Data hold time t
HD;DAT
50
ns
Data set-up time t
SU;DAT
50
Rise time of both SDA and SCL signals t
r
300
Fall time of both SDA and SCL signals t
f
100
Set-up time for STOP condition t
SU;STO
100
Bus free time between a STOP and START condition t
BUF
500
15