Datasheet

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DAC
+
+
Σ−∆
DAC
0 dB to −42 dB
(1.5 dB Steps).
−48 dB, −54 dB
Analog Sidetone
−9 dB to −27 dB
Σ−∆
ADC
0 dB to 42 dB
(1.5 dB Steps).
48 dB, 54 dB
Σ−∆
DAC
0 dB to −42 dB
(1.5 dB Steps).
−48 dB, −54 dB
Σ−∆
ADC
0 dB to 42 dB
(1.5 dB Steps).
48 dB, 54 dB
Analog Sidetone
−9 dB to −27 dB
1.35 V / 2.35
2 mA
SMARTDM

Serial Port
Internal Clock
Generator
Host Port
OUTP1
OUTM1
Line Output
600 Ω
OUTP2
OUTM2
150 Ω Output
INP2
INM2
Input
OUTP3
OUTM3
150 Ω Output
INP3
INM3
Input
MICI+
MICI−
Microphone
Input
INP1
INM1
Input
INP4
INM4
MICBIAS
LCDAC
MCLK FSD DOUT DIN SCLK FS M/S SDA SCL
CODEC 1 (Channel 1)
CODEC 2 (Channel 2)
Input
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Block Diagram - AIC24/25/24K
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