Datasheet

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POWER-CONSUMPTION
LCD DAC
Typical ADC performance With PGA Gain Setting Using FIR
(1)
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
AIC20/21/24/25/20k/24k
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
ADC (single channel) 5.7
DAC (single channel) Without drivers 3.5
Speaker driver
(1)
No signal 9.3
Handset driver No signal 2
Headset driver No signal 2
Lineout driver No signal 2 mW
Reference 2.3
Digital PLL off 3.4
Analog 4.6
PLL
Digital 1.8
Total Analog with all sections on No signal, PLL off 35.8
POWER DOWN CURRENT
Hardware power-down (no clock) 1
Analog, PLL off 2 µA
Software power-down
Digital 650
(1) The speaker driver is valid only for the AIC20/21/20k.
AIC20/21/20k
PARAMETER
MIN TYP MAX UNIT
V
O
Output range 0.35 2.35 V
Sampling rate 104 kHz
INL ±0.5 LSB
DNL ±0.25 LSB
V
S
Offset voltage ±25 mV
E
G
Gain error ±0.02 dB
PGA GAIN SETTING SNR THD SINAD UNIT
9 dB 83 90 81
18 dB 83 97 83 dB
24 dB 78 95 77
36 dB 72 95 72
(1) Test condition is a 1020-Hz input differential signal with an 8-kHz conversion rate. Input amplitude is given such that output of PGA is at
-3 dB level.
10