Datasheet
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Control Register 5B
(1)
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Table 5. A/D PGA Gain (continued)
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
0 0 0 0 0 0 1 1 ADC input PGA gain = -39 dB
0 0 0 0 0 0 1 0 ADC input PGA gain = -40 dB
0 0 0 0 0 0 0 1 ADC input PGA gain = -41 dB
0 0 0 0 0 0 0 0 ADC input PGA gain = -42 dB
D7 D6 D5 D4 D3 D2 D1 D0
0 1 DAGAIN
R/W R/W R/W R/W R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
Control Register 5B Bit Summary
(1) (2)
RESET
BIT NAME FUNCTION
VALUE
D7-D6 Control NA
Register 5B
D5-D0 DAGAIN 101010 D/A converter gain (see Table 6 )
(1) In register read operation, first read receives ADC gain value, second read receives DAC gain value, third receives register 5C and
fourth receives register 5D.
(2) PGA default value = 101010
b
(0dB) for both ADC and DAC.
Table 6. D/A PGA Gain
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
0 1 1 1 1 1 1 1 DAC input PGA gain = MUTE
0 1 1 1 1 1 1 0 DAC input PGA gain = 20 dB
0 1 1 1 1 1 0 1 DAC input PGA gain = 19 dB
0 1 1 1 1 1 0 0 DAC input PGA gain = 18 dB
0 1 1 1 1 0 1 1 DAC input PGA gain = 17 dB
0 1 1 1 1 0 1 0 DAC input PGA gain = 16 dB
0 1 1 1 1 0 0 1 DAC input PGA gain = 15 dB
0 1 1 1 1 0 0 0 DAC input PGA gain = 14 dB
0 1 1 1 0 1 1 1 DAC input PGA gain = 13 dB
0 1 1 1 0 1 1 0 DAC input PGA gain = 12 dB
0 1 1 1 0 1 0 1 DAC input PGA gain = 11 dB
0 1 1 1 0 1 0 0 DAC input PGA gain = 10 dB
0 1 1 1 0 0 1 1 DAC input PGA gain = 9 dB
0 1 1 1 0 0 1 0 DAC input PGA gain = 8 dB
0 1 1 1 0 0 0 1 DAC input PGA gain = 7 dB
0 1 1 1 0 0 0 0 DAC input PGA gain = 6 dB
0 1 1 0 1 1 1 1 DAC input PGA gain = 5 dB
0 1 1 0 1 1 1 0 DAC input PGA gain = 4 dB
0 1 1 0 1 1 0 1 DAC input PGA gain = 3 dB
0 1 1 0 1 1 0 0 DAC input PGA gain = 2 dB
0 1 1 0 1 0 1 1 DAC input PGA gain = 1 dB
0 1 1 0 1 0 1 0 DAC input PGA gain = 0 dB
0 1 1 0 1 0 0 1 DAC input PGA gain = -1 dB
0 1 1 0 1 0 0 0 DAC input PGA gain = -2 dB
0 1 1 0 0 1 1 1 DAC input PGA gain = -3 dB
44
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