Datasheet
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Control Register 5A
(5)
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Control Register 4 Bit Summary (continued)
RESET
BIT NAME FUNCTION
VALUE
D6-D0 MNP
(1) (2)
— Divider values of M, N, and P to be used in junction with the FSDIV bit for calculation of FS frequency
(3) (4)
according to the formula FS = MCLK / (16 x M x N x P)
⋅ M = 1,2, … ,128 Determined by D6-D0 with FSDIV = 1
D7-D0 = 10000000 M = 128
D7-D0 = 10000001 M = 1
to
D7-D0 = 11111111 M = 127
⋅ N = 1,2, … ,16 Determined by D6-D3 with FSDIV = 0
D7-D0 = 00000xxx N = 16
D7-D0 = 00001xxx N = 1
to
D7-D0 = 01111xxx N = 15
⋅ P = 1,2, … ,8 Determined by D2-D0 with FSDIV = 0
D7-D0 = 0xxxx000 P = 8
D7-D0 = 0xxxx001 P = 1
to
D7-D0 = 0xxxx111 P = 7
(1) It takes 2 sampling periods to update new values of M, N, and P.
(2) In register read operation, first read receives N and P values and second read receives M value.
(3) M(default) = 16, N(default) = 6, P(default) = 8
(4) If P = 8, the device enters the coarse sampling mode as described in operating frequencies section.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 ADGAIN
R/W R/W R/W R/W R/W R/W R/W R/W
(5) NOTE: R = Read, W = Write
Control Register 5A Bit Summary
(1) (2)
RESET
BIT NAME FUNCTION
VALUE
D7-D6 Control 00 ADC programmable gain amplifier
Register 5A
D5-D0 ADGAIN 101010 A/D converter gain (see Table 5 )
(1) In register read operation, first read receives ADC gain value, second read receives DAC gain value, third read receives register 5C
contents, and fourth read receives register 5D contents.
(2) PGA default value = 101010
b
(0dB) for both ADC and DAC.
Table 5. A/D PGA Gain
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
0 0 1 1 1 1 1 1 ADC input PGA gain = MUTE
0 0 1 1 1 1 1 0 ADC input PGA gain = 20 dB
0 0 1 1 1 1 0 1 ADC input PGA gain = 19 dB
0 0 1 1 1 1 0 0 ADC input PGA gain = 18 dB
0 0 1 1 1 0 1 1 ADC input PGA gain = 17 dB
0 0 1 1 1 0 1 0 ADC input PGA gain = 16 dB
0 0 1 1 1 0 0 1 ADC input PGA gain = 15 dB
0 0 1 1 1 0 0 0 ADC input PGA gain = 14 dB
0 0 1 1 0 1 1 1 ADC input PGA gain = 13 dB
0 0 1 1 0 1 1 0 ADC input PGA gain = 12 dB
0 0 1 1 0 1 0 1 ADC input PGA gain = 11 dB
0 0 1 1 0 1 0 0 ADC input PGA gain = 10 dB
0 0 1 1 0 0 1 1 ADC input PGA gain = 9 dB
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