Datasheet

www.ti.com
Control Register Content Description
Control Register 1
(1)
Control Register 2
(1)
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
D7 D6 D5 D4 D3 D2 D1 D0
ADOVF CX IIR DAOVF BIASV ALB DLB DAC16
R R/W R/W R R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
Control Register 1 Bit Summary
RESET
BIT NAME FUNCTION
VALUE
D7 ADOVF 0 ADC over flow. This bit indicates whether the ADC is overflow.
ADOVF = 0 No overflow.
ADOVF = 1 A/D is overflow.
D6 CX 0 Continuous data transfer mode. This bit selects between programming mode and continuous data transfer
mode.
CX = 0 Programming mode.
CX = 1 Continuous data transfer mode.
D5 IIR 0 IIR Filter. This bit selects between FIR and IIR for decimation/interpolation low-pass filter.
IIR = 0 FIR filter is selected.
IIR = 1 IIR filter is selected.
D4 DAOVF 0 DAC over flow. This bit indicates whether the DAC is overflow
DAOVF = 0 No overflow.
DAOVF = 1 DAC is overflow
D3 BIASV 0 Bias voltage. This bit selects the output voltage for BIAS pin
BIASV = 0 BIAS pin = 2.35 V
BIASV = 1 BIAS pin = 1.35 V
D2 ALB 0 Analog loop back
DLB = 0 Analog loopback disabled
DLB = 1 Analog loopback enabled
D1 DLB 0 Digital loop back
DLB = 0 Digital loopback disabled
DLB = 1 Digital loopback enabled
D0 DAC16 0 DAC 16-bit data format. This bit applies to the continuous data transfer mode only to enable the 16-bit data
format for DAC input.
DAC16 = 0 DAC input data length is 15 bits. Writing a 1 to the LSB of the DAC input to switch from
continuous data transfer mode to programming mode.
DAC16 = 1 DAC input data length is 16 bit.
D7 D6 D5 D4 D3 D2 D1 D0
TURBO DIFBP I
2
C6 I
2
C5 I
2
C4 GPO HPC
R/W R/W R/W R/W R/W R/W R/W R/W
(1) NOTE: R = Read, W = Write
Control Register 2 Bit Summary
RESET
BIT NAME FUNCTION
VALUE
D7 TURBO 0 Turbo mode. This bit is used to set the SCLK rate.
TURBO = 0 SCLK = (16 × FS × #Device × mode)
TURBO = 1 SCLK = MCLK/P (P is determined in register 4) (MCLK/P is valid only for master mode)
D6 DIFBP 0 Decimation/interpolation filter bypass. This bit is used to bypass both decimation and interpolation filters.
DIFBP = 0 Decimation/interpolation filters are operated.
DIFBP = 1 Decimation/interpolation filters are bypassed.
D5-D3 I
2
Cx 100 I
2
C device address. These three bits are programmable to define three MSBs of the I
2
C device address
(reset value is 100). These three bits are combined with the 4-bit SMARTDM device address to form 7-bit
I
2
C device address.
40
Submit Documentation Feedback