Datasheet

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Master FS
DIN
Master Slave2 Slave1 Slave0 Master Slave2 Slave1 Slave0 Master Slave2 Slave1 Slave0Slave0
Write
Command
Reg Addr (D15-D13)
R/W (D12)
Broadcast (D11)
D10-D8
001(1)
0
1
111
010(2)
0
1
111
100(4)
0
1
111
110(6)
0
1
111
Data Frame Control Frame
Time Slot
Register Map
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
A. NOTE: In this example, the broadcast operation (D11 = 1) is used to program the four control registers of Reg.1,
Reg.2, Reg.4, and Reg.6 in all 4 DSP codecs (Master, Slave2, Slave1, and Slave0) shown in Figure 33 . These
registers are programmed during the same frame.
Figure 41. Control Frame Data Format
Bits D15 through D13 represent the control register address that is written with data carried in D7 through D0.
Bit D12 determines a read or a write cycle to the addressed register. When D12 = 0, a write cycle is selected.
When D12 = 1, a read cycle is selected. Bit D11 controls the broadcast mode as described above, in which the
broadcast mode is enabled if D11 is set to 1. Always write 1s to the bits D10 through D8.
Table 3 shows the register map.
Table 3. Register Map
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register Address RW BC 1 1 1 Control Register Content
Table 4. Register Addresses
REGISTER NO. D15 D14 D13 REGISTER NAME
0 0 0 0 No operation
1 0 0 1 control 1
2 0 1 0 control 2
3 0 1 1 control 3
4 1 0 0 control 4
5 1 0 1 control 5
6 1 1 0 control 6
39
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