Datasheet

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Master Slave2 Slave1 Slave0 Slave2Master

Master FS

DIN/DOUT

Master FSD,

Slave 2 FS

Slave 2 FSD,

Slave 1 FS

Slave 1 FSD,

Slave 0 FS

Slave 0 FSD,

(see Note)

Programming Mode

SCLK

DIN

DOUT

16-Bit DAC Data Register Data Write

16-Bit ADC Data Register Data Read

Slot Number 0

Slot Number 1

TLV320AIC12, TLV320AIC13

TLV320AIC14, TLV320AIC15

TLV320AIC12K, TLV320AIC14K

SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007

A. NOTE: Slave 0 FSD should be pulled high for stand-alone-master or cascade configuration. FSD must be pulled low

for stand-alone-slave configuration.

Figure 33. Master-Slave Frame-Sync Timing in Continuous Data Transfer Mode

In the programming mode, the FS signal starts the input/output data stream. Each period of FS contains two

frames as shown in Figure 34 and Figure 35 : data frame and control frame. The data frame contains data

transmitted from the ADC or to the DAC. The control frame contains data to program the AIC1xs control

registers. The SMARTDM automatically sets the number of time slots per frame equal to 2 times the number of

AIC1x codecs in the interface. Each time slot contains 16-bit data. The SCLK is used to perform data transfer for

the serial interface between the AIC1x codecs and the DSP. The frequency of SCLK varies depending on the

selected mode of serial interface. In the stand alone-mode, there are 32 SCLKs (or two time slots) per sampling

period. In the master-slave cascade mode, the number of SLCKs equals 32 x (Number of codecs in the

cascade). The digital output data from the ADC is taken from DOUT. The digital input data for the DAC is

applied to DIN. The synchronization clock for the serial communication data and the frame-sync is taken from

SCLK. The frame-sync signal that starts the ADC and DAC data transfer interval is taken from FS. The

SMARTDM also provides a turbo mode, in which the FS's frequency is always the device's sampling frequency,

but SCLK is running at a much higher speed. Thus, there are more than 32 SCLKs per sampling period, in

which the data frame and control frame occupy only the first 32 SCLKs from the falling edge of the frame-sync

FS (see the Digital Interface Section for more details).

Figure 34. Standard Operation/Programming Mode: Stand-Alone Timing

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