Datasheet

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SCLK
FSD
(Output)
DIN/DOUT
(16 Bit)
MSB LSB
D15 D14
D2 D1
0 1 14 1513
D0
FS
16 SCLKs
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
MCLK
DIN
DOUT
FS
SCLK
Slave 2 Slave 1 Slave 0Master
MCLK
DIN
DOUT
FSD
SCLK
FSD FSD
FS
CLKOUT
DX
DR
FSX
FSR
CLKX
CLKR
TMS320C5x
M/S M/S M/S M/S
FSD
IOVDD
1 kΩ
100 MHz Max
IOVDD
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Asynchronous Sampling (Codecs in cascade are sampled at different sampling frequency)
The 'AIC1x SMARTDM supports a different sampling frequency between the codecs in cascade connecting to a
single serial port. All codecs are required to have a common frame synch frequency. The FS signal is calculated
using step 1. The desired sampling frequencies of the individual codecs are then calculated using bits D2-D0 of
control register 3 as shown in step 2 and step 3.
1. FS = MCLK ÷ (16 × M × N × P)
2. FS = n1 × fs1 (n1 = 1,2, 8 defined in the control register 3 of CODEC1)
3. FS = n2 × fs2 (n2 = 1,2, 8 defined in the control register 3 of CODEC2)
The DSP should transfer data at the common FS rate used by the serial interface. The task of decimating and
interpolating the data suitably for each codec is left to the DSP.
Figure 31. Timing Diagram for FSD Output
Figure 32. Cascade Connection (To DSP Interface)
33
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