Datasheet

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Digital Interface
SCLK
FS
DIN/DOUT
(16 Bit)
MSB LSB
D15 D14
D1 D0
0 1 15 1614
D15
16 SCLKs
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Clock Source (MCLK, SCLK)
MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughout
the device. SCLK is the bit clock used to receive and transmit data synchronously. When the device is in the
master mode, SCLK and FS are output and derived from MCLK in order to provide clocking the serial
communications between the device and a digital signal processor (DSP). When in the slave mode, SCLK and
FS are inputs. In the non-turbo mode (TURBO = 0), SCLK frequency is defined by:
• SCLK = (16 × FS × #Devices × mode)
Where:
• FS is the frame-sync frequency. #Device is the number of the device in cascade. Mode is equal to 1 for
continuous data transfer mode and 2 for programming mode.
In turbo mode, see the Turbo Mode Operation section of this data sheet.
Serial Data Out (DOUT)
DOUT is placed in the high-impedance state after transmission of the LSB is completed. In data frame, the data
word is the ADC conversion result. In the control frame, the data is the register read results when requested by
the read/write (R/W) bit. If a register read is not requested, the low eight bits of the secondary word are all
zeroes. Valid data on DOUT is taken from the high-impedance state by the falling edge of frame-sync (FS). The
first bit transmitted on the falling edge of FS is the MSB of valid data.
Serial Data In (DIN)
The data format of DIN is the same as that of DOUT, in which MSB is received first on the falling edge of FS. In
a data frame, the data word is the input digital signal to the DAC channel. If (15+1)-bit data format is used, the
LSB (D0) is set to 1 to switch from the continuous data transfer mode to the programming mode. In a control
frame, the data is the control and configuration data that sets the device for a particular function as described in
the Control Register Programming section.
Frame-Sync FS
The frame-sync signal (FS) indicates the device is ready to send and receive data. The FS is an output if the
M/S pin is connected to HI (master mode), and an input if the M/S pin is connected to LO (slave mode).
The start of valid data is synchronized on the falling edge of the FS signal. In nonturbo mode, the FS signal
must be present every (16 SCLK × mode). However, in turbo mode, the number of SCLK per FS cycle can vary.
The frequency of FS is defined as the sampling rate of the TLV320AIC1x and derived from the master clock,
MCLK, as follows (see Operating Frequencies section for details):
• FS = MCLK ÷ (16 × P × N × M)
Figure 30. Timing Diagram of FS
Cascade Mode and Frame-Sync Delayed (FSD)
In cascade mode, the DSP should be in slave mode, it receives all frame-sync pulses from the master though
31
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