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IIR/FIR Control
Overflow Flags
IIR/FIR Bypass Mode
System Reset and Power Management
Software and Hardware Reset
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Functional Description (continued)
Analog Output Configuration (continued)
SPEAKER DRIVER CONFIGURATION NO. OF SPEAKER DRIVERS ON MIN LOAD
Differential 2 32- Ω
The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input analog
signal has exceeded the range of internal decimation filter calculations. The interpolation IIR/FIR filter sets an
overflow flag (bit D4) of control register 1 indicating that the digital input has exceeded the range of internal
interpolation filter calculations. When the IIR/FIR overflow flag is set in the register, it remains set until the user
reads the register. Reading this value resets the overflow flag. These flags need to be reset after power-up by
reading the register. If FIR/IIR overflow occurs, the input signal is attenuated by either the PGA or some other
method.
An option is provided to bypass IIR/FIR filter sections of the decimation filter and the interpolation filter. This
mode is selected through bit D6 of control register 2 and effectively increases the frequency of the FS signal to
four times normal output rate of the IIR/FIR-filter. For example, for a normal sampling rate of 8 Ksps (i.e., FS =
8 kHz) with IIR/FIR, if the IIR/FIR is bypassed, the frequency of FS is readjusted to 4 × 8 kHz = 32 kHz. The sinc
filters of the two paths can not be bypassed. A maximum of eight devices in cascade can be supported in the
IIR/FIR bypassed mode.
In this mode , the ADC channel outputs data which has been decimated only until 4Fs. Similarly DAC channel
input needs to be preinterpolated to 4Fs before being given to the device. This mode allows users the flexibility
to implement their own filter in DSP for decimation and interpolation. M should be a multiple of 4 during IIR/FIR
Bypass mode. The frequency responses of the IIR/FIR bypass modes are shown in Figure 14 and Figure 15 .
The TLV320AIC1x resets internal counters and registers in response to either of two events:
• A low-going reset pulse is applied to terminal RESET
• A 1 is written to the programmable software reset bits (D5 of control register 3)
• NOTE: The TLV320AIC1x requires a power-up reset applied to the RESET pin before normal operation is
started.
Either event resets the control registers and clears all sequential circuits in the device. The H/W RESET (active
low) signal is at least 6 master clock periods long. As soon as the RESET input is applied, the TLV320AIC1x
enters the initialization cycle that lasts for 132 MCLKs, during which the serial port of the DSP must be tristated.
The initialization sequence performed by the 'AIC1x is known as auto cascade detection (ACD). ACD is a
mechanism that allows a device to know its address in a cascade chain. Up to 16 'AIC1x devices can be
cascaded together. The master device is the first device on the chain (i.e. the FS of the master is connected to
the FS of the DSP). During ACD, each device gets to know the number of devices in the chain as well as its
relative position in the chain. This is done on hardware reset. Therefore, after power up, a hardware reset must
be done. ACD requires 132 MCLKs after reset to complete operation. The number of MCLKs is independent of
the number of devices in the chain. Adjacent devices in the chain have their FS and FSD pins connected to
each other. The master device FS is connected to the FS pin of the DSP. The FSD pin on the last device in the
chain is pulled high. The master device has the highest address (i.e. 0, the next device in the chain has an
address of 1, followed by 2 etc.).
During the first 64 MCLKs, FS is configured as an output and FSD as an input. During the next 64 MCLKs, FS is
configured as an input and FSD as an output. The master device always has FS configured as an output and
the last slave in the cascade (i.e. channel with address 0) always has FSD configured as an input.
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