Datasheet

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MCLK
1/P
X8
(DLL)
1/(MN)
128FS
(no_devxmode)/(MNP)
SCLK
1/(16xmodexno_dev)
FS
en_dll
M=1-128
N=1-16
P =1-8
WhenP =8,DLL(PLL)isenabled
devnum=numberofdevicesincascade
mode=1(forcontiniousdatatranfermode)
SCLKmaynotbeanuniformclockdependinguponvaluesofdevnum,mode,andMNP
Digital
mode=2(forprogrammingmode)
*
*
FS +
20.48 MHz
(16 10 16 1)
+ 8 kHz
Internal Architecture
Analog Low-Pass Filter
Sigma-Delta ADC
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Functional Description (continued)
Figure 20. AIC1x Clock Tree Architecture
6. Both equation of FS require that the following conditions be met:
– (M × N × P) ≥ (devnum × mode) if the FIR/IIR filter is not bypassed.
– [Integer (M ÷ 4) × N × P] ≥ (devnum × mode) if the FIR/IIR filter is bypassed.
Where:
– devnum is the number of codec channels connecting in cascade mode.
– mode is equal to 1 for continuous data transfer mode and 2 for programming mode.
7. If the DAC OSR is set to 512, then M needs to be a multiple of 4. If the DAC OSR is set to 256,
then M needs to be a multiple of 2. M can take any value between 1 and 128 if the OSR is set to
128.
EXAMPLE:
The MCLK that comes from the DSP 'C5402 CLKOUT equals to 20.48 MHz, and the conversion rate
of 8 kHz is desired. First, set P = 1 to satisfy condition step 5 above so that (MCLK ÷ P) = 20.48 MHz
÷ 1 = 20.48 MHz. Next, pick M = 10 and N = 16 to satisfy step 6 above and derive 8 kHz for FS.
The built-in analog low-pass filter is a two-pole filter that has a 20-dB attenuation at 1 MHz.
The analog-to-digital converter is a sigma-delta modulator with 128-x oversampling. The ADC provides
high-resolution, low-noise performance using oversampling techniques. Due to the oversampling employed, only
single pole R-C filters are required on the analog inputs.
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