Datasheet

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SDA
SCL
t
SU;STO
t
BUF
t
r
t
HD;STA
t
SU;STA
t
HIGH
t
HD;DAT
t
HD;STA
t
LOW
t
f
t
r
t
f
t
SU;OAT
Parameter Measurement Information
-160
-140
-120
-100
-80
-60
-40
-20
0
0 1000 2000 3000
Amplitude-dB
f-Frequency-Hz
500 1500 2500 3500 4000
SamplingRateat8kHz
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Figure 3. I
2
C / S
2
C Timing
TEST CONDITIONS MIN MAX UNIT
t
SCL
SCL clock frequency 0 900 kHz
t
HD;STA
Hold time (repeated START condition. After this 100 ns
period, the first clock pulse is generated.
t
LOW
Low period of the SCL clock 560 ns
t
HIGH
High period of the SCL clock 560 ns
t
SU;STA
Set-up time for a repeated START condition C
L
= 20 pF 100 ns
t
HD;DAT
Data hold time 50 ns
t
SU;DAT
Data set-up time 50 ns
t
r
Rise time of both SDA and SCL signals 300 ns
t
f
Fall time of both SDA and SCL signals 100 ns
t
SU;STO
Set-up time for STOP condition 100 ns
t
BUF
Bus free time between a STOP and START condition 500 ns
Figure 4. FFT—ADC Channel (-1 dB Input)
16
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