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Timing Requirements
t
h1
2.4 V
MCLK
RESET
2.4 V
t
su1
2.4 V
t
wL
t
wH
t
d1
t
d2
t
d1
t
d2
t
en
t
d3
t
dis
t
su2
t
h2
D15
D15
SCLK
FS
FSD
DOUT
DIN
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Figure 1. Hardware Reset Timing
Figure 2. Serial Communication Timing
TEST CONDITIONS MIN TYP MAX UNIT
t
wH
Pulse duration, MCLK high 5
t
wL
Pulse duration, MCLK low 5
Setup time, RESET, before MCLK high
t
su1
3
(see Figure 1 )
t
h1
Hold time, RESET, after MCLK high (see Figure 1 ) 2
t
d1
Delay time, SCLK ↑ to FS/FSD ↓ C
L
= 20 pF 5 ns
t
d2
Delay time, SCLK ↑ to FS/FSD ↑ 5
t
d3
Delay time, SCLK ↑ to DOUT 15
t
en
Enable time, SCLK ↑ to DOUT 15
t
dis
Disable time, SCLK ↑ to DOUT 15
t
su2
Setup time, DIN, before SCLK ↓ 10
t
h2
Hold time, DIN, after SCLK ↓ 10
15
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