Datasheet

TLV320AIC1110
SLAS359 – DECEMBER 2001
6
www.ti.com
detailed description
power on/reset
The power for the various digital and analog circuits is separated to improve the noise performance of the
device. An external reset must be applied to the active low RESET
terminal to assure reset upon power on and
to bring the device to an operational state. After the initial power-on sequence, the device can be functionally
powered up and powered down by writing to the power control register through the I
2
C interface. The device
has a pin-selectable power up in the default mode option. The hardwired pin-selectable PWRUPSEL function
allows the PCM codec to power up in the default mode and to be used without a microcontroller.
reference
A precision band gap reference voltage is generated internally and supplies all required voltage references to
operate the transmit and receive channels. The reference system also supplies bias voltage for use with an
electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting
at terminal REXT.
I
2
C control interface
The I
2
C interface is a two-wire bidirectional serial interface. The I
2
C interface controls the PCM codec by writing
data to seven control registers:
 Power control
 Mode control
 Transmit PGA and sidetone control
 Receive PGA gain and volume control
 DTMF routing
 Tone selection control
 Auxiliary control
There are two power-up modes which may be selected at the PWRUPSEL terminal: (1) The PWRUPSEL state
(V
DD
at terminal 20) causes the device to power up in the default mode when power is applied. Without an I
2
C
interface or controlling device, the programmable functions are fixed at the default gain levels, and functions
such as the sidetone and DTMF are not accessible. (2) The PWRUPSEL state (ground at terminal 20) causes
the device to go to a power-down state when power is applied. In this mode, an I
2
C interface is required to power
up the device.
phase-locked loop (PLL)
The phase-lock loop generates the internal clock frequency required for digital filters and modulators by phase
locking to 2.048-MHz master clock input.
PCM interface
The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is
transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK can be tied directly
to the 128-kHz or 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or
derived from the master clock and used as an interrupt to the host controller.
microphone amplifiers
The microphone input is a switchable interface for two differential microphone inputs. The first stage is a
low-noise differential amplifier that provides a gain of 23.5 dB. The second-stage amplifier has a selectable gain
of 6 dB or 18 dB.