Datasheet

TLV320AIC1110
SLAS359 – DECEMBER 2001
33
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PRINCIPLES OF OPERATION
register map (continued)
Transmit PGA and sidetone control register: Address (02)HEX
Bit definitions:
7 6 5 4 3 2 1 0 DEFINITION
X TP3 TP2 TP1 TP0 ST2 ST1 ST0 See Table 2 and Table 4
0 1 0 0 0 0 0 0 Default setting
Receive volume control register: Address (03)HEX
Bit definitions:
7 6 5 4 3 2 1 0 DEFINITION
RP3 RP2 RP1 RP0 RV3 RV2 RV1 RV0 See Table 3 and Table 5
1 0 1 0 0 0 0 0 Default setting
High tone selection control register: Address (04)HEX
Bit definitions:
7 6 5 4 3 2 1 0 DEFINITION
X X X X X X X X DTMF (see Table 7)
0 0 0 0 0 0 0 0 Default setting
Low tone selection control register: Address (05)HEX
Bit definitions :
7 6 5 4 3 2 1 0 DEFINITION
X X X X X X X X DTMF (see Table 7)
0 0 0 0 0 0 0 0 Default setting
Auxiliary register: Address (06)HEX
Bit definitions:
7 6 5 4 3 2 1 0 DEFINITION
0 0 0 0 0 0 0 0 Default
X X X X X X X 0 MCLK is set to 2.048 MHz
X X X X X X X 1 MCLK is set to 128 MHz
X X X X X X 0 X Analog switch output is set to OUT2
X X X X X X 1 X Analog switch output is set to OUT1
X X X X 0 0 X X Low tone frequency resolution is set to 7.8125 Hz
X X X X 0 1 X X Low tone frequency resolution is set to 15.625 Hz
X X X X 1 0 X X Low tone frequency resolution is set to 31.250 Hz
X X 0 0 X X X X High tone frequency resolution is set to 7.8125 Hz
X X 0 1 X X X X High tone frequency resolution is set to 15.625 Hz
X X 1 0 X X X X High tone frequency resolution is set to 31.250 Hz
X 0 X X X X X X Receiver channel gain, RXPGA2 is equal to 0 dB, voice mode only
X 1 X X X X X X Receiver channel gain, RXPGA2 is equal to 6 dB, voice mode only
0 X X X X X X X MCLK detector is powered ON
1 X X X X X X X MCLK detector is powered OFF