Datasheet

TLV320AIC1110
SLAS359 – DECEMBER 2001
18
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timing requirements (continued)
I
2
C bus timing requirements (see Figure 3)
PARAMETER MIN MAX UNIT
SCL Clock frequency 400 kHz
t
w(SCLH)
Pulse duration, SCL high 600 ns
t
w(SCLL)
Pulse duration, SCL low 1300 ns
t
h(STA)
Hold time, SCL high after SDA↓ (repeated START condition)
†
600 ns
t
su(STA)
Setup time, for SCL high before SDA↓ repeated START condition 600 ns
t
h(DAT)
Hold time, SDA valid after SCL low 0 ns
t
su(DAT)
Setup time, SDA valid before SCL↑ 100 ns
t
su(STO)
Setup time, STOP condition 600 ns
t
w(SDAT)
Pulse duration, SDA high (bus free time) 1300 ns
t
r
Rise time (SDA and SCL) 300 ns
t
f
Fall time (SDA and SCL) 300 ns
†
After this period, the first block pulse is generated.
switching characteristics over recommended ranges of supply voltages and operating free-air
temperature
propagation delay times, C
L(max)
= 10 pF (see Figure 1)
PARAMETER MIN MAX UNIT
t
pd1
PCMCLK bit 1 high to PCMO bit 1 valid 35 ns
t
pd2
PCMCLK high to PCMO valid, bits 2 to n 35 ns
t
pd3
PCMCLK bit n low to PCMO bit n Hi-Z 30 ns
DTMF generator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DTMF high to low tone relative amplitude (preemphasis) 1.5 2 2.5 dB
Tone frequency accuracy (for DTMF) Resolution of 7.8125 Hz –1.5% 1.5%
Harmonic distortion
Measured from lower tone group to
highest parasitic
–20 dB
MICBIAS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Load impedance (bias mode) 5 kΩ