Datasheet

TLV320AIC1110
SLAS359 – DECEMBER 2001
17
www.ti.com
timing requirements
clock (2.048-MHz CLK)
PARAMETER MIN NOM MAX UNIT
t
t
Transition time, MCLK 10 ns
f
(mclk)
MCLK frequency 2.048 MHz
MCLK jitter 37%
Number of PCMCLK clock cycles per PCMSYN frame 256 256 cycles
t
c(PCMCLK)
PCMCLK clock period 156 488 512 ns
Duty cycle, PCMCLK 45% 50% 68%
transmit (2.048-MHz CLK) (see Figure 1)
PARAMETER MIN MAX UNIT
t
su(PCMSYN)
Setup time, PCMSYN high before falling edge of PCMCLK 20 t
c(PCMCLK)
–20
ns
t
h(PCMSYN)
Hold time, PCMSYN high after falling edge of PCMCLK 20 t
c(PCMCLK)
–20
ns
receive (2.048-MHz CLK) (see Figure 2)
PARAMETER MIN MAX UNIT
t
su(PCSYN)
Setup time, PCMSYN high before falling edge of PCMCLK 20 t
c(PCMCLK)
–20 ns
t
h(PCSYN)
Hold time, PCMSYN high after falling edge of PCMCLK 20 t
c(PCMCLK)
–20 ns
t
su(PCMI)
Setup time, PCMI high or low before falling edge of PCMCLK 20 ns
t
h(PCMI)
Hold time, PCMI high or low after falling edge of PCMCLK 20 ns
clock (128-kHz CLK)
PARAMETER MIN NOM MAX UNIT
t
t
Transition time, MCLK 10 ns
f
(mclk)
MCLK frequency 128 kHz
MCLK jitter 5%
Number of PCMCLK clock cycles per PCMSYN frame 16 16
t
c(PCMCLK)
PCMCLK clock period 742.19 781.25 820.31 ns
Duty cycle, PCMCLK 40% 50% 60%
t
c(PCMSYN)
PCMSYN clock period 125 µs
Duty cycle, PCMCLK 49.5% 50% 50.5%
transmit (128-kHz CLK) (see Figure 5)
PARAMETER MIN MAX UNIT
t
su(PCMSYN)
Setup time, PCMSYN high before PCMCLK↑ 20 t
c(PCMCLK)
/4
ns
t
h(PCMSYN)
Hold time, PCMSYN high after PCMCLK↓ 20 t
c(PCMCLK)
/4
ns
t
v(PCMO)
Data valid time after the rising edge of PCMSYNC 50 ns
receive (128-kHz CLK) (see Figure 4)
PARAMETER MIN MAX UNIT
t
su(PCSYN)
Setup time, PCMSYN high before rising edge of PCMCLK 20 t
c(PCMCLK)
/4 ns
t
h(PCSYN)
Hold time, PCMSYN high after falling edge of PCMCLK 20 t
c(PCMCLK)
/4 ns
t
su(PCMI)
Setup time, PCMI high or low before falling edge of PCMCLK 20 ns
t
h(PCMI)
Hold time, PCMI high or low after falling edge of PCMCLK 20 ns