Datasheet

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SLAS357 − DECEMBER 2001
9
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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted) (continued)
power supply rejection
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply voltage rejection, transmit channel
MICIN−, MICIN+ = 0 V, V
DD
= 2.7 V + 100 mV
pp,
f = 1 kHz, Resistor tolerance of 1%
−74 −50 dB
Supply voltage rejection, receive channel
(differential)
PCM code = positive zero, V
DD
= 2.7 V + 100 mV
pp
,
f = 1 kHz, Resistor tolerance of 1%
−80 −65 dB
crosstalk attenuation, linear mode selected
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Crosstalk attenuation, transmit-to-receive
(differential)
MICIN−, MICIN+ = 0 dB, f = 300 Hz to 3400 Hz measured
differentially between EAROUT− and EAROUT+
70 dB
Crosstalk attenuation, receive-to-transmit PCMI = 0 dBm0, f = 300 Hz to 3400 Hz measured at PCMO 70 dB
timing requirements
clock
MIN NOM MAX UNIT
t
t
Transition time, MCLK 10 ns
f
mclk
MCLK frequency 2.048 MHz
MCLK jitter 37%
MCLK clock cycles per PCMSYN frame 256 256 cycles
transmit (see Figure 1)
MIN MAX UNIT
t
su(PCMSYN)
Setup time, PCMSYN high before MCLK ↓ 20 t
c(MCLK)
−20
ns
t
h(PCMSYN)
Hold time, PCMSYN high after MCLK ↓ 20 t
c(MCLK)
−20
receive (see Figure 2)
MIN MAX UNIT
t
su(PCSYN)
Setup time, PCMSYN high before MCLK ↓ 20 t
c(MCLK)
−20 ns
t
h(PCSYN)
Hold time, PCMSYN high after MCLK ↓ 20 t
c(MCLK)
−20 ns
t
su(PCMI)
Setup time, PCMI high or low before MCLK ↓ 20 ns
t
h(PCMI)
Hold time, PCMI high or low after MCLK ↓ 20 ns
switching characteristics over recommended operating conditions, C
L
max = 10 pF (see Figure 1)
MIN MAX UNIT
t
pd1
Propagation delay time, MCLK bit 1 high to PCMO bit 1 valid 35 ns
t
pd2
Propagation delay time, MCLK high to PCMO valid, bits 2 to n 35 ns
t
pd3
Propagation delay time, MCLK bit n low to PCMO bit n Hi-Z 30 ns