Datasheet

A–2
A.1 Control Register 1
Table A–3. Register Map
D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
ovf – – – – – – – Decimator FIR overflow flag
– 1 – – – – – – Enable HYBRID receiver/MIC amp (A1)
– 0 – – – – – – Disable HYBRID/MIC amp (A1)
– – 1 – – – – – Bypass antialiasing filter
– – 0 – – – – – Enable antialiasing filter
– – – 1 – – – – Select AUXP and AUXM for ADC
– – – 0 – – – – Select INP and INM for ADC
– – – – 1 – – – Software reset
– – – – 0 – – – Default
– – – – – 1 – – Bypass decimation/interpolation FIR filter
– – – – – 0 – Normal operation with FIR filter
– – – – – – 1 – Enable HYBRID transmitter/MIC amps (A3,A4)
– – – – – – 0 – Disable HYBRID transmitter/MIC amps (A3,A4)
– – – – – – – 1 16-bit data format for DAC
– – – – – – – 0 15-bit data + LSB format for DAC
Default value: 00000000
NOTE: A software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write a 0 to end the
master reset operation.
Enabling the D6 bit automatically selects AUX channel for the ADC input.
A.2 Control Register 2
Table A–4. Control Register 2
D7 D6 D5 D4 D3 D2 D1 D0 DIVIDE VALUE
1 – – – – – – – Low-power operation mode
0 – – – – – – – Normal operation mode
– 1 – – – – – – S–D modulator stops
– 0 – – – – – – S–D modulator runs
– – R – – – – – Reserved
– – – 1 1 1 1 1 Frequency Divider N = 31
– – – • •
– – –
• •
– – – • •
– – – 0 0 0 0 1 Frequency Divider N = 1
– – – 0 0 0 0 0 Frequency Divider N = 32
Default value: 00000000
NOTE: The serial port interface always gluelessly works with the DSP. The following modes will not produce
50% duty cycle SCLK:
1. If the number of devices in cascade >4 and N is an odd number (i.e., N = 1, 3, 5,...)
2. If the number of devices in cascade ≤4, FIR is bypassed, and N ≠ 4, 8, 12, 16, 20, 24, 28, 32