Datasheet

3–3

3.2.1 Register Programming

All register programming occurs during secondary communication through DIN or ALTI, and data are latched and

valid on the falling edge of the SCLK during the frame-sync signal. If the default value of a particular register is desired,

that register does not need to be addressed during the secondary communication interval. The NOOP command

(DS15-DS8 all set to 0) addresses the pseudo-register (register 0), and no register programming takes place during

the communication.

In addition, each register can be read back through DOUT during secondary communications by setting the read bit

(D12) to 1. When a register is in the read mode, no data can be written to the register during this cycle. A subsequent

secondary communication is required to return this register to the write mode.

For example, if the contents of control register 1 of device 3 are desired to be read out from DOUT, the following

procedure must be performed through DIN:

• Request secondary communication by setting either D0 = 1(software request), or FC = high (hardware

request) during the primary communication interval.

• During the secondary communication interval (FS), send data in through DIN using the following format:

Device Address RW Register Address X Register Content

0 1 1 1 0 0 1 x x x x x x x x x

DS15 DS0

• Then, during the same frame, the following data is read from DOUT; the last 8 bits of DOUT contains

Device Address RW Register Address X Register Content

0 1 1 x x x x x d d d d d d d d

DS15 DS0

Figure 3–3 is the timing diagram of this procedure.

DOUT

DIN

Low 8 Bit (D0 – D7) Is

the Content of Register

Figure 3–3. Device 3/Register 1 Read Operation Timing Diagram