Datasheet

1–8
DAC channel DAC channel refers to all signal-processing circuits between the digital data word applied
to DIN and the differential output analog signal available at OUTP and OUTM.
Host A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or MCLK.
PGA Programmable gain amplifier
FIR Finite-duration impulse response
DCSI Direct configuration serial interface with host
1.7 Register Functional Summary
There are five control registers which are used as follows:
Register 0 The no-op register. Addressing register 0 allows secondary-communication request without altering any
other registers.
Register 1 Control register 1. The data in this register has the following functions:
• Produce the output flag to indicate a decimator FIR filter overflow (read cycle only)
• Enable of general-purpose operational amplifiers A1, A3, and A4
• Enable/bypass ADCs analog antialiasing filter
• Select normal or auxiliary analog input
• Control 16-bit or (15+1)-bit mode of DAC operation
• Activate software reset
• Enable/bypass the decimator FIR filter
• Enable/bypass the interpolator FIR filter
Register 2 Control register 2. The data in this register has the following functions:
• Control of the low-power mode that converts data at the rate of 8 ksps
• Control of the N-divide register that determines the filter clock rate and sample period
Register 3 Control register 3. The data in this register has the following functions:
• Software power down
• Selection of analog loopback, digital loopback, and event monitor mode
• Control of continuous data transfer mode
• Control of the value of one-bit general-purpose output flag
• Control the output of FLAG pin
• Enable/disable ADC path
• Enable/disable DAC path
• Control of 16-bit or (15+1)-bit mode of ADC operation
Register 4 Control register 4. The data in this register has the following functions:
• Control of the 4-bit gain of input PGA
• Control of the 4-bit gain of output PGA