!" Data Manual December 2001 HPA Data Acquisition SLWS093F
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Contents Section 1 2 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . . . .
3 4 iv 2.7.3 Frame-Sync (FS) Function—Master Mode . . . . . . . . . . . . . 2.7.4 Frame-Sync (FS) Function—Slave Mode . . . . . . . . . . . . . . 2.7.5 Frame-Sync Delayed (FSD) Function, Cascade Mode . . . 2.8 Multiplexed Analog Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.1 Multiplexed Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 6 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1 Appendix A—Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–1 List of Illustrations Figure Title 2–1 Timing Sequence of ADC Channel (Primary Communication Only) . . . . . .
3–9 Direct Configuration Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–10 Continuous Data Transfer Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–11 Primary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . . 3–12 Secondary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . 3–13 Direct Communication DCSI Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1 FC, FS and FSD Timing . . . . . . . .
1 Introduction The TLV320AIC10 provides high resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. It allows 2-to-1 MUX inputs with built-in antialiasing filter and amplification for general-purpose applications such as telephone hybrid interface, electret microphone preamp, etc. Both IN and AUX inputs accept normal analog signals.
1–2 • Glueless serial port interface to DSPs (TI TMS320Cxx, SPI, or standard DSPs) • Automatic cascading detection (ACD) makes cascade programming simple and allows up to 8 devices to be connected in cascade. • On-fly reconfiguration modes include secondary-communication mode and direct-configuration mode (host interface).
1.2 Functional Block Diagram Receiver or MIC Amp AURXFP SW5 SW6 SW4 + AURXCP – SW2 A1 SW3 Note: Switches SWx are Controlled by Bit D6 of Control Register 1.
1.3 Terminal Assignments INM INP AVSS AV DD1 NC VMID AV SS NC AV SS NC FILT NC PFB PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 AURXFP AURXM AURXCP DTXOP DTXOM DTXIP DTXIM OUTP OUTM M0 M1 PWRDWN 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 RESET DV SS DV DD1 DOUT DIN NC SCLK MCLK FSD FS FLAG FC 13 14 15 16 17 18 19 20 21 22 23 24 NOTE: All NC pins should be left unconnected.
1.
1.5 Terminal Functions TERMINALS NAME I/O NO. DESCRIPTION PFB GQE I/O ALTIN 26 G9 I Serial input in the event monitor mode. Tie this pin to low if not used. AURXCP 3 C1 I Receiver-path/GP amplifier noninverting input. It needs to be connected to AVSS if not used. AURXM 2 C2 I Receiver-path amplifier A1 inverting input, or inverting input to auxiliary analog input. It needs to be connected to AVSS if not used. Can also be used for general-purpose amplification.
1.5 Terminal Functions (Continued) TERMINALS NAME I/O NO. PFB GQE I/O DESCRIPTION MCLK 20 J5 I Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit. M/S 27 F8 I Master/slave select input. When M/S is high, the device is the master, and when is low, it is a slave. NC 18, 28, 31, 32, 35, 36, 37, 39, 41, 44 A6, A7, C9, C8, F9 OUTM 9 F2 O DACs inverting output. OUTM is functionally identical with and complementary to OUTP.
DAC channel DAC channel refers to all signal-processing circuits between the digital data word applied to DIN and the differential output analog signal available at OUTP and OUTM. Host A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or MCLK. PGA Programmable gain amplifier FIR Finite-duration impulse response DCSI Direct configuration serial interface with host 1.
2 Functional Description 2.1 Device Functions 2.1.1 Operating Frequencies The sampling frequency represented by the frequency of the primary communication is derived from the master clock (MCLK) input with the following equation: Fs = Sampling (conversion) frequency = MCLK/(256 × N), N = 1, 2..., 32 The inverse of the sampling frequency is the time between the falling edges of two successive primary frame-sync signals. This time is the conversion period.
Primary Secondary 16 SCLKs 16 SCLKs 16–bit ADC Data M/S+ Register Data/ M/S+ All 0 (See Note A) 15–bit ADC Data + M/S M/S+ Register Data/ M/S+ All 0 (See Note A) Primary FS DOUT (16-bit) DOUT (15+1-bit) # SCLKs (See Note B) # SCLKs Per Sampling Period (See Note C) NOTES: A. M/S bit (D15) in the secondary communication is used to indicate whether the register data (address and content) come from a master device or a slave device if read bit is set.
0 1 …… SCLK 15 14 16 16 SCLKs …… FS DIN (16-bit) D15 D14 …… D1 D0 MSB DIN (15+1-bit) D15 LSB D14 …… D1 D0=0 (See Note A) MSB LSB NOTE A: d0 = 0 means no secondary-communication request (software secondary-request control, see Section 3.2). Figure 2–3.
2.1.4 MIC Input The auxiliary inputs (AURXFP, AURXCP, and AURXM) can be programmed to interface with a microphone such as an electret microphone, as illustrated in Figure 2.5, by writing a 1 to bit D6 and D4 of control register 1. Enabling MIC input with DG automatically selects AURx channel for ADC input. TLV320AIC10 10 kΩ 0.1 µF 10 kΩ Electret Microphone AURXFP AURXM AURXCP – + S2D AntiAliasing Filter 1 kΩ MIC_BIAS VMID PGA SigmaDelta ADC Vref Figure 2–5. Typical Microphone Interface 2.
2.1.10 Analog and Digital Loopback The analog and digital loopbacks provide a means of testing the modem data ADC/DAC channels and can be used for in-circuit system level tests. The analog loopback routes the DAC low-pass filter output into the analog input where it is then converted by the ADC to a digital word. The digital loopback routes the ADC output to the DAC input on the device. Analog loopback is enabled by writing 01 to bits D7 and D6 respectively in control register 3.
2.2 Reset and Power-Down Functions 2.2.1 Software and Hardware Reset The TLV320AIC10 resets the internal counters and registers in response to either of two events: • A low-going reset pulse is applied to terminal RESET • A 1 is written to the programmable-software reset bit (D3 of control register 1) Either event resets the control registers and clears all the sequential circuits in the device. Reset signals should be at least six master-clock periods long.
2.3 Clock Source MCLK is the external master-clock input. The clock circuit generates and distributes the necessary clocks throughout the device. When the device is in the master mode, SCLK and FS are output and derived from MCLK in order to provide clocking of the serial communications between the device and a DSP (digital signal processor). When in the slave mode, SCLK and FS are all inputs.
The TLV320AIC10 has four serial-interface modes that support most modern DSP engines. This modes can be selected by M0 and M1. In mode 0 (Figure 2–8), FS is one-bit wide and it is active high one SCLK period before the first bit (MSB) of each data transmission. In modes 1 (Figure 2–9) and 2 (Figure 2–10), the TLV320AIC10 operates as a slave to interface with an SPI master in which FS is the SPISEL that determines the sampling rate. SCLK needs to be free-running.
0 1 …… SCLK 15 14 16 16 SCLKs …… FS DIN/DOUT (16-bit) D15 D14 …… D1 MSB D0 LSB Figure 2–11. Timing Diagram for the FS Frame Mode (M1M0 = 11) NOTE: In frame mode, if AIC10 is in slave mode, DIN/DOUT should be delayed by one SCLK from the falling edge of FS. 2.7.1 Frame-Sync (FS) Function—Continuous-Transfer Mode (Master Only) Writing a 1 to bit D5 of control register 3 enables the continuous-transfer mode.
2.7.4 Frame-Sync (FS) Function—Slave Mode The slave mode is selected by connecting pin M/S to LO. The frame-sync timing is generated externally by the master, as shown in Figure 2–13 (that is, FSD) and is applied to FS of the slave to control the ADC and DAC timing. FS (Master to DSP) MP SP MS SS MP FSD (Master) to FS (Slave) 32 SCLKs NOTE: MP: master primary (master-device data is transferred during this period, the DOUT of the slave device is in high-impedance state).
Master FS P P P P S S M S2 S1 S0 M S2 S Master FSD, Slave 2 FS 32 SCLKs Slave 2 FSD, Slave 1 FS 32 SCLKs Slave 1 FSD, Slave 0 FS 32 SCLKs Slave 0 FSD (See Note) 32 SCLKs Figure 2–15. Master-Slave Frame-Sync Timing 2.8 Multiplexed Analog Input and Output The two differential analog inputs (INP and INM, or AUXP and AUXM) are multiplexed into the sigma-delta modulator. The performance of the AUX channel is similar to the normal-input channel.
2.8.2 Analog Output OUTP and OUTM are differential outputs and can typically drive a 600-Ω load directly. Figure 2–17 shows the circuit when the load is ground-referenced. 10 k Ω +5 V 10 k Ω – OUTM + 10 k Ω TLE2062 OUTP –5 V Load 10 k Ω Figure 2–17. Differential Output Drive (Ground-Referenced) 2.8.
3 Serial Communications DOUT, DIN, SCLK, SXCLK, FS, and Fc are the serial communication signals. SCLK is used to perform internal processing and data transfer for serial interface between AIC10 and DSP. In the pulse/frame FS mode, there are 256 SCLKs per sampling period (512 if there are more than 4 devices in cascade). The digital-output data for the ADC is taken from DOUT. The digital-input data for the DAC is applied to DIN.
3.2 Secondary Serial Communication Secondary serial communication is used to read or write 16-bit words that program both the options and the circuit configurations of the device. Register programming always occurs during secondary communication. Four primary and secondary communication cycles are requested to program the four registers. If the default value for a particular register is desired, then the register addressing can be omitted during secondary communications.
3.2.1 Register Programming All register programming occurs during secondary communication through DIN or ALTI, and data are latched and valid on the falling edge of the SCLK during the frame-sync signal. If the default value of a particular register is desired, that register does not need to be addressed during the secondary communication interval. The NOOP command (DS15-DS8 all set to 0) addresses the pseudo-register (register 0), and no register programming takes place during the communication.
To program control register 1, the following procedure must be performed through DIN: • Request secondary communication by setting either D0=1(software request), or FC = high (hardware request) during the primary communication interval. • At the secondary communication interval (FS), send data in the following format through DIN: Device Address 0 1 RW 1 0 Register Address X 0 x 0 1 Register Content d d d d d d d DS15 d DS0 • The following is the data out of DOUT.
P P Master FS M P S2 P S1 S S0 S M S S2 S S1 P S0 M (FC pulse needs to be inserted any time within the primary communication) FC (See Note) NOTES: A. FC of master device and slave devices should be connected together B. Primary communication interval = 256 SCLKs if cascading devices < 5 C. Primary communication interval = 512 SCLKs if cascading devices > 4 Figure 3–6. Output When Hardware Secondary Serial Communication Is Requested (Three Slaves) 3.2.
DVDD 1 kΩ CLKX0 DX0 DCSI M/S FSX1 FSR1 DCSI FS M/S DVDD FSD DGND FS DX1 DIN DIN DR1 DOUT DOUT SCLK SCLK 1 kΩ FSD CLKX1 CLKR1 TMS320C54XX TLV320AIC10 TLV320AIC10 (a) Direct Configuration Between C54 and AIC10 MCLK DVDD (Use Pullup Resistor if SDO Is 3-State Serial Bus) 1 kΩ MCLK DCSI SDO BFSX0 BFSR0 FS DVDD BDX0 DIN BDR0 DOUT FSD SCLK M/S 1 kΩ BCLKX0 DVDD CLKIN BCLKR0 TMS320C5402 TLV320AIC10 (b) Direct Configuration for Host Interface Figure 3–8.
SCLK D15 D14 D13 D12 D11 D10 D9 DCSI Start Bit Device =0 Address D8 D7 D6 Register Address D5 D4 D3 D2 D1 D0 Register Data Stop Bit =1 Figure 3–9. Direct Configuration Mode Timing To program control register 1 of device 3, send data in with the following format through DCSI: SB 0 Device Address 0 1 1 Register Address X 0 x 0 1 Register Content x x x x x x x D15 x D0 3.
3.5 DIN and DOUT Data Format 3.5.1 Primary Serial Communication DIN and DOUT Data Format DIN (15 + 1)-Bit Mode D15 – D1 D0 A/D & D/A Data DOUT (15 + 1)-Bit Mode Secondary Communication Request D0 D15 – D1 M/S Bit DIN 16-Bit Mode D15 – D0 A/D & D/A Data DOUT 16-Bit Mode D15 – D0 Figure 3–11. Primary Communication DIN and DOUT Data Format 3.5.
4 Specifications 4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted)† Supply voltage range, DVDD, AVDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V Output voltage range, all digital output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to DVDD+0.3 V Input voltage range, all digital input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 ADC Path Filter, Fs = 8 kHz (see Note 2) PARAMETER Filter gain relative to gain at 1020 Hz TEST CONDITIONS MIN TYP MAX 0 Hz to 300 Hz –0.5 0.2 300 Hz to 3 kHz –0.5 0.25 3.3 kHz –0.5 0.3 3.6 kHz –3 4 kHz –35 ≥ 4.4 kHz –74 UNIT dB NOTE 2: The filter gain outside of the passband is measured with respect to the gain at 1024 Hz. The analog input test signal is a sine wave with 0 dB = 4 VI(PP) as the reference level for the analog input signal.
4.3.4 ADC Channel Characteristics PARAMETER VI(PP) TEST CONDITIONS MIN 4 UNIT Dynamic range VI = –3 dB 82 dB 87 dB VI = –1 dB at 1020 Hz 0.6 dB ±15 mV Intrachannel isolation Gain error CMRR Common-mode rejection ratio at INM, INP or AUXM, AUXP ADC converter offset error Idle channel noise (on-chip reference) VI = –1 dB at 1020 Hz VINP,INM = 0 V Input resistance TA = 25°C 80 25 V dB 70 35 Channel delay 4.3.
4.3.6.3 DAC Signal-to-Distortion + Noise When Load is 600 Ω (see Note 5) PARAMETER THD+N TEST CONDITIONS Signal to total harmonic distortion + noise Signal-to-total MIN TYP VI = 0 dB VI = –3 dB 70 77 73 78 VI = –9 dB VI = –40 dB 70 78 35 42 MAX UNIT dB NOTE 5: The test condition is the digital equivalent of a 1020-Hz input signal with an 8-kHz conversion rate. The test is measured at output of application schematic low-pass filter. The test is conducted in 16-bit mode. 4.3.
4.3.10 Power Supply 4.3.10.1 Low-Power Mode (set control register bit D7 to 1) PARAMETER PD Power dissipation IDD (analog) Supply current IDD (digital) Supply current TEST CONDITIONS MIN All sections on, VDD = 3.3 V All sections on, AVDD = 3.3 V TYP MAX UNIT 39.3 mW 9.7 mA 11.2 mA All sections on, AVDD = 3.3 V 2.3 mA All sections on, AVDD = 5 V 4.9 mA All sections on, AVDD = 5 V 4.3.10.
4–6
5 Parameter Measurement Information 2.4 V SCLK td(CH–FL) td(CH–FH) FC/FS/FSD 0.8 V Figure 5–1. FC, FS, and FSD Timing td(3) tw(H) MCLK tw(L) SCLK td(2) td(1) FS tdls ten DOUT D15 D14 tsu DIN D15 D14 th Figure 5–2.
AMPLITUDE vs FREQUENCY 0 fs = 8 kHz Input = –3 dB Amplitude – dB –30 –60 –90 –120 –150 0 500 1000 1500 2000 2500 3000 3500 4000 f – Frequency – Hz Figure 5–3. FFT–ADC Channel AMPLITUDE vs FREQUENCY 0 fs = 16 kHz Input = –3 dB Amplitude – dB –30 –60 –90 –120 –150 0 1000 2000 3000 4000 5000 6000 f – Frequency – Hz Figure 5–4.
AMPLITUDE vs FREQUENCY 0 fs = 8 kHz Input = –3 dB Amplitude – dB –30 –60 –90 –120 –150 0 500 1000 1500 2000 2500 3000 3500 4000 f – Frequency – Hz Figure 5–5. FFT–DAC Channel AMPLITUDE vs FREQUENCY 0 fs = 16 kHz Input = –3 dB Amplitude – dB –30 –60 –90 –120 –150 0 1000 2000 3000 4000 5000 6000 7000 8000 f – Frequency – Hz Figure 5–6.
AMPLITUDE vs FREQUENCY 0 fs = 8 kHz Input = –1 dB Amplitude – dB –30 –60 –90 –120 –150 0 500 1000 1500 2000 2500 3000 3500 4000 f – Frequency – Hz Figure 5–7. FFT–ADC Channel AMPLITUDE vs FREQUENCY 0 fs = 16 kHz Input = –1 dB Amplitude – dB –30 –60 –90 –120 –150 0 1000 2000 3000 4000 5000 6000 f – Frequency – Hz Figure 5–8.
AMPLITUDE vs FREQUENCY 0 fs = 8 kHz Input = –0 dB Amplitude – dB –30 –60 –90 –120 –150 0 500 1000 1500 2000 2500 3000 3500 4000 f – Frequency – Hz Figure 5–9. FFT–DAC Channel AMPLITUDE vs FREQUENCY 0 fs = 16 kHz Input = –0 dB Amplitude – dB –30 –60 –90 –120 –150 0 1000 2000 3000 4000 5000 6000 7000 8000 f – Frequency – Hz Figure 5–10.
5–6
6 Mechanical Information PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°–ā7° 1,05 0,95 Seating Plane 1,20 MAX 0,75 0,45 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
GQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY 5,10 SQ 4,90 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,68 0,62 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,35 0,25 NOTES: A. B. C. D. ∅ 0,05 M All linear dimensions are in millimeters. This drawing is subject to change without notice. MicroStar Junior BGA configuration Falls within JEDEC MO-225 MicroStar Junior is a trademark of Texas Instruments.
Appendix A Register Set Bits D15 through D13 represent the device address in the cascade set by the automatic cascade detection described in Section 2.1.13. In cascading, the master is the device directly connected to the DSP. For example, if there are four devices in the cascade, as shown in row 4 of Table A-1 and in Section 2.7.5, the device address D15-D13 of the master will have a binary value of 011.
A.1 Control Register 1 Table A–3.
A.3 Control Register 3 Table A–5.
A.4 Control Register 4 Table A–6.
TLV320AIC10 AURXFP AURXM AURXCP AntiAliasing Filter PGA SigmaDelta ADC Vref VMID DTXOP DTXIM DTXIP DTXOM OUTP PGA Low Pass Filter SigmaDelta DAC OUTM Figure A–1.
TLV320AIC10 AURXFP AURXM AURXCP AntiAliasing Filter PGA SigmaDelta ADC Vref VMID DTXOP DTXIM DTXIP DTXOM OUTP PGA OUTM Figure A–2.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV320AIC10IGQER Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR GQE 80 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 5.3 5.3 1.5 8.0 W Pin1 (mm) Quadrant 12.
PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320AIC10IGQER BGA MICROSTAR JUNIOR GQE 80 2500 340.5 333.0 20.
