Datasheet

1–3
1.2 Functional Block Diagram
Sigma–
Delta
ADC
Sinc
Filter
Low
Pass
Filter
Sigma–
Delta
DAC
ADREFP
ADREFM
MCLK
Interface
Circuit
Div
256xN
DIN
M/S
FSD
FS
SCLK
M0
M1
OUTP
OUTM
PGA
PGA
DOUT
Internal Clock Circuit
FIR
Filter
Analog
Loopback
Decimation Filter
Anti–
Aliasing
Filter
VMID
@ 5 mA
V
ALTI
FLAG
FC
DCSI
DAREFP
DAREFM
MUX
AURXM
AURXFP
INM
INP
AURXCP
1.5 V
or
2.5V
DTXOP
DTXIM
Receiver or MIC Amp
Transmitter Amp
DTXIP
DTXOM
+
–
+
–
–
+
A3
A4
A2
A1
Sinc
Filter
FIR
Filter
Interpolation Filter
Digital
Loopback
SW4
SW5
SW6
SW2 SW3
SW1
Note: Switches SWx are Controlled by Bit D6 of Control Register 1.
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