Datasheet

A–1
Appendix A
Register Set
Bits D15 through D13 represent the device address in the cascade set by the automatic cascade detection described
in Section 2.1.13. In cascading, the master is the device directly connected to the DSP. For example, if there are four
devices in the cascade, as shown in row 4 of Table A-1 and in Section 2.7.5, the device address D15-D13 of the master
will have a binary value of 011. The other three slaves addresses are 010, 001, and 000, corresponding to their
positions in the cascade. The device address for a stand-alone device is always 000. Bits D11 through D8 comprise
the address of the register that is written with data carried in D7 through D0. D12 determines a read or write cycle
to the addressed register; a low selects a write cycle.
The following table shows the register map.
REGISTER MAP
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Device Address RW Register Address X Control Register Content
Table A–1. Device Address
D15 D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14
Device Address R/W Register Adress X Register Content
Device 0
REGISTER MAP
000
000
000
000
000
000
000
000
Device 1
001
001
001
001
001
001
001
Device 2
010
010
010
010
010
010
Device 3
011
011
011
011
011
Device 4
100
100
100
100
Device 5
101
101
101
Device 6
110
110
Device 7
1118
7
6
5
4
3
1
2
DEVICE ADDRESS (D15–D13)# Devices
in Cascade
Table A–2. Register Address
REGISTER NO. D11 D10 D9 REGISTER NAME
0 0 0 0 No operation
1 0 0 1 Control 1
2 0 1 0 Control 2
3 0 1 1 Control 3
4 1 0 0 Control 4