Datasheet

4–5
4.3.10 Power Supply
4.3.10.1Low-Power Mode (set control register bit D7 to 1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
P
D
Power dissipation All sections on, V
DD
= 3.3 V 39.3 mW
I (analog)
Supply current
All sections on, AV
DD
= 3.3 V 9.7 mA
I
DD
(analog) Supply current
All sections on, AV
DD
= 5 V
11.2 mA
I (digital)
Supply current
All sections on, AV
DD
= 3.3 V 2.3 mA
I
DD
(digital) Supply current
All sections on, AV
DD
= 5 V 4.9 mA
4.3.10.2Normal Operation
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
P
D
Power dissipation All sections on, V
DD
= 3.3 V 48.5 mW
All sections on, AV
DD
= 3.3 V 13.6 mA
I (analog)
Supply current
All sections on, AV
DD
= 5 V 14.8 mA
I
DD
(analog) Supply current
Power down, AV
DD
= 3.3 V
3 µA
Power down, AV
DD
= 5 V 11 µA
All sections on, AV
DD
= 3.3 V 1.1 mA
I
DD
(digital)
Su
pp
ly current
All sections on, AV
DD
= 5 V 2.3 mA
I
DD
(digital) Supply current
Power down, AV
DD
= 3.3 V
0.15 mA
Power down, AV
DD
= 5 V 0.6 mA
4.4 Timing Requirements (see Parameter Measurement Information)
4.4.1 Master Mode Timing Requirements
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
t
d(1)
Delay time, SCLK↑ to FS↓ 5 ns
t
d(2)
Delay time, SCLK↑ to DOUT 15 ns
t
su
Setup time, DIN, before SCLK low 5 ns
t
h
Hold time, DIN, after SCLK high 1/2T+5 ns
t
en
Enable time, FS↓ to DOUT 1/2T+5 ns
t
dis
Disable time, FS↑ to DOUT Hi-Z
C
L
= 20 pF
5 ns
t
d(3)
Delay time, MCLK↓ to SCLK↑
L
10 ns
t
d(CH-FL)
Delay time, SCLK high to FS/FSD high (see Figure 5-1) 5 ns
t
d(CH-FH)
Delay time, SCLK high to FS/FSD high 5 ns
t
w(H)
Pulse duration, MCLK high 12.5 ns
t
w(L)
Pulse duration, MCLK low 12.5 ns