Datasheet

2–11

32 SCLKs

Master FS

S S

Master FSD,

Slave 2 FS

Slave 2 FSD,

Slave 1 FS

Slave 1 FSD,

Slave 0 FS

Slave 0 FSD

(See Note)

32 SCLKs

Figure 2–15. Master-Slave Frame-Sync Timing

2.8 Multiplexed Analog Input and Output

The two differential analog inputs (INP and INM, or AUXP and AUXM) are multiplexed into the sigma-delta modulator.

The performance of the AUX channel is similar to the normal-input channel. The gain of the input amplifiers is set

through control register 4.

2.8.1 Multiplexed Analog Input

To produce excellent common-mode rejection of unwanted-signal performance, the analog signal is processed

differentially until it is converted to digital data. The signal applied to the INM and INP terminals should be differential

to preserve the device specifications. The signal source driving the analog inputs (INP and INM, or AUXP and AUXM)

should have a low source impedance to attain the lowest noise performance and accuracy. To obtain maximum

dynamic range, the signal should be ac-coupled to the input terminal. The analog input signal is self-biased to the

mid-supply. Bits D3 and D4 of control register 1 select these input sources. The default condition self-biases the input,

since the register default value selects INP and INM as the sources for the ADC.

TLV320AIC10

INP

INM

Figure 2–16. INP and INM Internal Self-Biased (AV

/2) Circuit