Datasheet

2–9
D0
16 SCLKs
SCLK
FS
DIN/DOUT
(16-bit)
D1
MSB LSB
D15
0 1 15 16
D14
……
……
……
14
Figure 2–11. Timing Diagram for the FS Frame Mode (M1M0 = 11)
NOTE: In frame mode, if AIC10 is in slave mode, DIN/DOUT should be delayed by one SCLK from the falling edge of FS.
2.7.1 Frame-Sync (FS) Function—Continuous-Transfer Mode (Master Only)
Writing a 1 to bit D5 of control register 3 enables the continuous-transfer mode. In this mode, the data bits are
transmitted and received contiguously with no inactivity between bits at the very next FS, and no further frame sync
FSs are generated. Secondary communication is not available. To disable the continuous transfer mode, use the
direct-configuration mode (see Section 3.3) or reset the device.
2.7.2 Frame-Sync (FS) Function—Fast-Transfer Mode (Slave Only)
By connecting the fast clock to the SCLK pin, data can be transmitted and received at a higher rate than 256 x Fs
in the slave mode for a stand-alone AIC10.
2.7.3 Frame-Sync (FS) Function—Master Mode
The master mode in the TLV320AIC10 is selected by connecting pin M/S pin to HI. In the master mode, the
TLV320AIC10 generates the frame-sync signal (FS) to the DSP that goes low on the rising edge of SCLK and remains
low during a 16-bit data transfer.
DIN/DOUT
Primary Secondary
16 SCLKs
Primary
16 SCLKs
FS
(see Note B)
FS
(see Note A)
Primary Primary
NOTES: A. Primary and secondary serial communications
B. Primary serial communication only
Figure 2–12. Master Device Frame-Sync Signal With Primary and Secondary Communication ( No Slaves)