Datasheet
2–3
D0
16 SCLKs
SCLK
FS
DIN
(16-bit)
DIN
(15+1-bit)
D1
MSB LSB
LSB
D15
D0=0D1
0 1 15 16
MSB
D15
D14
D14
……
……
……
……
14
(See Note A)
NOTE A: d0 = 0 means no secondary-communication request (software secondary-request control, see Section 3.2).
Figure 2–3. Timing Sequence of DAC Channel (Primary Communication Only)
FS
DIN (16-bit)
(See Note A)
DIN
(15+1-bit)
Primary Secondary
16 SCLKs
# SCLKs Between Sampling Period (See Note D)
16–bit DAC Data
# SCLKs Between
Primary
16 SCLKs
FS (Primary) and
FS (Secondary)
(See Note C)
15–bit DAC Data +
D0 = 1 (See Note B)
Register Read/Write
Register Read/Write
NOTES: A. FC has to be set high for a secondary communication request when 16-bit DAC data format is used (see Section 3.2).
B. D0 = 1 means secondary communication request (software secondary request control, see Section 3.2)
C. The number of SCLKs between FS (Primary) and FS (Secondary) is 128 if cascading devices are less than 5, or 256 if cascading
devices are greater than 4.
D. The number of SCLKs per data sampling period is 256 if cascading devices are less than 5, or 512 if cascading devices are greater
than 4.
Figure 2–4. Timing Sequence of DAC Channel (Primary and Secondary Communication)