Datasheet

AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS
WCLK
BCLK
DOUT
t (DO-BCLK)
d
t (DO-WS)
d
t (WS)
d
t
r
t
f
TLV320ADC3101
www.ti.com ...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
All specifications at 25 ° C, DVDD = 1.8 V
IOVDD = 1.8 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
d
(WS) BCLK/WCLK delay time 20 15 ns
t
d
(DO-WS) BCLK/WCLK to DOUT delay time 25 20 ns
t
d
(DO-BCLK) BCLK to DOUT delay time 20 15 ns
t
r
Rise time 20 15 ns
t
f
Fall time 20 15 ns
NOTE: All timing specifications are measured at characterization.
Figure 2. I
2
S/LJF/RJF Timing in Master Mode
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