Datasheet

TLV320ADC3101
SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ...................................................................................................................................... www.ti.com
Page 0 / Register 61: ADC Processing Block Selection
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D5 000 Reserved. Do not write any value other than reset value.
D4 – D0 0 0001 0 0000: ADC miniDSP programmable instruction mode enabled.
0 0001: Select ADC Signal Processing Block PRB_R1
0 0010: Select ADC Signal Processing Block PRB_R2
0 0011: Select ADC Signal Processing Block PRB_R3
0 0100: Select ADC Signal Processing Block PRB_R4
0 0101: Select ADC Signal Processing Block PRB_R5
0 0110: Select ADC Signal Processing Block PRB_R6
0 0111: Select ADC Signal Processing Block PRB_R7
0 1000: Select ADC Signal Processing Block PRB_R8
0 1001: Select ADC Signal Processing Block PRB_R9
0 1010: Select ADC Signal Processing Block PRB_R10
0 1011: Select ADC Signal Processing Block PRB_R11
0 1100: Select ADC Signal Processing Block PRB_R12
0 1101: Select ADC Signal Processing Block PRB_R13
0 1110: Select ADC Signal Processing Block PRB_R14
0 1111: Select ADC Signal Processing Block PRB_R15
1 0000: Select ADC Signal Processing Block PRB_R16
1 0001: Select ADC Signal Processing Block PRB_R17
1 0010: Select ADC Signal Processing Block PRB_R18
1 0011 – 1 1111: Reserved. Do not use.
Page 0 / Register 62: Programmable Instruction-Mode Control Bits
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R 0 Reserved. Do not write any value other than reset value.
D6 R/W 0 ADC miniDSP engine auxiliary control bit A, which can be used for conditional instructions like JMP
D5 R/W 0 ADC miniDSP engine auxiliary control bit B, which can be used for conditional instructions like JMP
D4 R/W 0 0: ADC instruction-counter reset at the start of the new frame is enabled.
1: ADC instruction-counter reset at the start of the new frame is disabled.
D3 – D0 R 0000 Reserved. Do not write any value other than reset value.
Page 0 / Register 63 Through Page 0 / Register 79: Reserved
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D0 R XXXX XXXX Reserved. Do not write to these registers.
Page 0 / Register 80: ADC Digital-Microphone Polarity Select
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D2 R 0000 00 Reserved. Do not write any value other than reset value.
D1 R/W 0 0: Capture left channel digital microphone data on rising edge of ADC modulator clock.
1: Capture left channel digital microphone data on falling edge of ADC modulator clock.
D0 R/W 0 0: Capture right channel digital microphone data on rising edge of ADC modulator clock.
1: Capture right channel digital microphone data on falling edge of ADC modulator clock.
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