Datasheet

TLV320ADC3101
www.ti.com ...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
Page 0 / Register 33: Secondary Audio Interface Control 3
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK
D6 R/W 0 0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock
D5 – D4 R/W 01 00: Reserved. Do not use.
01: Primary WCLK output = internally generated ADC_f
S
clock (Default)
10: Primary WCLK output = secondary WCLK
11: Reserved. Do not use.
D3 – D2 R/W 00 00: Secondary WCLK output = primary WCLK
01: Reserved. Do not use.
10: Secondary WCLK output = internally generated ADC_f
S
clock
11: Reserved. Do not use.
D1 – D0 R 00 Reserved. Do not write any value other than reset value.
Page 0 / Register 34: I
2
S Sync
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Internal logic is enabled to detect the I
2
C hang and react accordingly.
1: Internal logic is disabled to detect the I
2
C hang.
D6
(1)
R/W 0 0: I
2
C hang is not detected.
1: I
2
C hang detected flag. Once set get cleared only after reading this register.
D5 R/W 0 0: I
2
C general-call address is ignored.
1: Device accepts I
2
C general-call address.
D4 – D2 R 000 Reserved. Do not write any value other than reset value.
D1 R/W 0 0: Re-sync logic is disabled for ADC.
1: Re-sync stereo ADC with codec interface if the group delay changed by more than ± ADC_f
S
/4.
D0 R/W 0 0: Re-sync is done without soft-muting the channel for ADC.
1: Re-sync is done by internally soft-muting the channel for ADC.
(1) Read-only bits. Writing any value to this is not used anywhere.
Page 0 / Register 35: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D0 R XXXX XXXX Reserved. Do not write to this register.
Page 0 / Register 36: ADC Flag Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7
(1)
R 0 0: Left ADC PGA , applied gain ≠ programmed gain
1: Left ADC PGA , applied gain = programmed gain
D6
(1)
R 0 0: Left ADC powered down
1: Left ADC powered up
D5
(2)
R 0 0: Left AGC not saturated
1: Left AGC applied gain = maximum applicable gain by left AGC
D4 R 0 Reserved. Do not write any value other than reset value.
D3
(1)
R 0 0: Right ADC PGA , applied gain ≠ programmed gain
1: Right ADC PGA , applied gain = programmed gain
D2
(1)
R 0 0: Right ADC powered down
1: Right ADC powered up
D1
(2)
R 0 0: Right AGC not saturated
1: Right AGC applied gain = maximum applicable gain by right AGC
D0 R 0 Reserved. Do not write any value other than reset value.
(1) Read-only bits. Writing any value to this bit is not used anywhere.
(2) Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
freshly again.
Copyright © 2008 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 51
Product Folder Link(s) :TLV320ADC3101