Datasheet

TLV320ADC3101
www.ti.com ...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
Page / Register Map (continued)
58 ADC sync control 2
59 ADC CIC filter gain control
60 Reserved
61 ADC processing block selection
62 Programmable instruction mode control bits
63 – 79 Reserved
80 Digital microphone polarity control
81 ADC digital
82 ADC fine volume control
83 Left ADC volume control
84 Right ADC volume control
85 ADC phase compensation
86 Left AGC control 1
87 Left AGC control 2
88 Left AGC maximum gain
89 Left AGC attack time
90 Left AGC decay time
91 Left AGC noise debounce
92 Left AGC signal debounce
93 Left AGC gain
94 Right AGC control 1
95 Right AGC control 2
96 Right AGC maximum gain
97 Right AGC attack time
98 Right AGC decay time
99 Right AGC noise debounce
100 Right AGC signal debounce
101 Right AGC gain
102 – 127 Reserved
PAGE1: (ADC Routing, PGA, Power-Controls, Etc.)
Register No. Register Name
0 Page control register
1 – 25 Reserved
26 Dither control
27 – 50 Reserved
51 MICBIAS control
52 Left ADC input selection for left PGA
53 Reserved
54 Left ADC input selection for left PGA
55 Right ADC input selection for right PGA
56 Reserved
57 Right ADC input selection for right PGA
58 Reserved
59 Left analog PGA setting
60 Right analog PGA setting
61 ADC low-current modes
62 ADC analog PGA flags
63 – 127 Reserved
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