Datasheet

TLV320ADC3101
SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ...................................................................................................................................... www.ti.com
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Page / Register Map
PAGE 0: (Clock Multipliers and Dividers, Serial Interfaces, Flags, Interrupts and Programming of GPIOs)
Register No. Register Name
0 Page control register
1 S/W RESET
2 Reserved
3 Reserved
4 Clock-gen multiplexing
5 PLL P and R-VAL
6 PLL J-VAL
7 PLL D-VAL MSB
8 PLL D-VAL LSB
9 – 17 Reserved
18 ADC NADC
19 ADC MADC
20 ADC AOSR
21 ADC IADC
22 ADC miniDSP engine decimation
23 – 24 Reserved
25 CLKOUT MUX
26 CLKOUT M Divider
27 ADC audio interface control 1
28 Data slot offset programmability 1 (Ch_Offset_1)
29 ADC interface control 2
30 BCLK N Divider
31 Secondary audio interface control 1
32 Secondary audo interface control 2
33 Secondary audio interface control 3
34 I
2
S sync
35 Reserved
36 ADC flag register
37 Data slot offset progammability 2 (Ch_Offset_2)
38 I
2
S TDM control register
39 – 41 Reserved
42 Interrupt flags (overflow)
43 Interrupt flags (overflow)
44 Reserved
45 Interrupt flags – ADC
46 Reserved
47 Interrupt flags – ADC
48 INT1 interrupt control
49 INT2 interrupt control
50 Reserved
51 DMCLK/GPIO2 control
52 DMDIN/GPIO1 control
53 DOUT (out pin) control
54 – 56 Reserved
57 ADC sync control 1
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