Datasheet

Left ADC
CIC Filter
Right ADC
CIC Filter
Digital
Volume
P0/R83–R84
miniDSP
DMDIN
DMCLK
DMCLK
DMDIN
D S-
D S-
ADC_MOD_CLK
LEFT
or
RIGHT
ADC_MOD_CLK
DMDINorDMCLK
LEFT
or
RIGHT
LEFT
or
RIGHT
LEFT
or
RIGHT
LEFT
or
RIGHT
LEFT
or
RIGHT
CONTROL REGISTERS
TLV320ADC3101
www.ti.com ...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
Figure 47. Digital Microphone in TLV320ADC3101
The TLV320ADC3101 outputs internal clock ADC_MOD_CLK on the DMCLK pin (page 0 / register 51,
bits D5 – D2) or DMDIN pin (page 0 / register 52, bits D5 – D2). This clock can be connected to the external digital
microphone device. The single-bit output of the external digital microphone device can be connected to DMDIN
or DMCLK pins. Internally, the TLV320ADC3101 latches the steady value of data on a selectable edge (page 0 /
register 80, bit D1) of ADC_MOD_CLK for the left ADC channel, and the steady value of data on a selectable
edge (page 0 / register 80, bit D0) for the right ADC channel.
Figure 48. Timing Diagram for Digital Microphone Interface
The digital-microphone mode can be selectively enabled for only-left, only-right, or stereo channels. When the
digital microphone mode is enabled, the analog section of the ADC can be powered down and bypassed for
power efficiency. The AOSR value for the ADC channel must be configured to select the desired decimation ratio
to be achieved based on the external digital microphone properties. Following the CIC filter is a stereo digital
volume control, where left and right volume are adjusted by writing to page 0 / register 83 and page 0 /
register 84, respectively. Next is the miniDSP, where the processing blocks can be selected or custom
processing can be used. The processed digital microphone signal is then output at the DOUT pin.
The control registers for the TLV320ADC3101 are described in detail as follows. All registers are 8 bits in width,
with D7 referring to the most-significant bit of each register and D0 referring to the least-significant bit.
Pages 0, 1, 4, 5, and 32 – 47 are available. All other pages are reserved. Do not read from or write to reserved
pages.
The procedure for register access is:
• Select page N (Write data N to register 0 regardless of the current page number).
• Read or write data from/to valid registers in page N.
• Select new page M (Write data M to register 0 regardless of the current page number).
• Read or write data from/to valid registers in page M.
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