Datasheet

MICBIAS GENERATION
ADC Decimation Filtering and Signal Processing
Processing Blocks
TLV320ADC3101
www.ti.com ...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
The TLV320ADC3101 includes two programmable microphone bias outputs (MICBIAS1, MICBIAS2), each
capable of providing output voltages of 2 V or 2.5 V (both derived from the on-chip band-gap voltage) with 4-mA
output-current drive capability. In addition, the MICBIAS outputs may be programmed to be switched to AVDD
directly through an on-chip switch, or it can be powered down completely when not needed, for power savings.
This function is controlled by register programming in page 1 / register 51.
The TLV320ADC3101 ADC channel includes a built-in digital decimation filter to process the oversampled data
from the delta-sigma modulator to generate digital data at the Nyquist sampling rate with high dynamic range.
The decimation filter can be chosen from three different types, depending on the required frequency response,
group delay and sampling rate.
The TLV320ADC3101 offers a range of processing blocks which implement various signal processing capabilities
along with decimation filtering. These processing blocks give users the choice of how much and what type of
signal processing they may use and which decimation filter is applied.
The signal processing blocks available are:
• First-order IIR
• Scalable number of biquad filters
• Variable-tap FIR filter
• AGC
The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in
combination with various signal processing effects such as audio effects and frequency shaping. The available
first-order IIR, biquad, and FIR filters have fully user-programmable coefficients. ADC processing blocks can be
selected by writing to page 0 / register 61. The default (reset) processing block is PRB_R1.
Table 6. ADC Processing Blocks
Decimation First-Order Number of
Processing Required AOSR Instruction
Channel FIR
Blocks Value Count
Filter IIR Available Biquads
PRB_R1 Stereo A Yes 0 No 128, 64 188
PRB_R2 Stereo A Yes 5 No 128, 64 240
PRB_R3 Stereo A Yes 0 25-tap 128, 64 236
PRB_R4 Right A Yes 0 No 128, 64 96
PRB_R5 Right A Yes 5 No 128, 64 120
PRB_R6 Right A Yes 0 25-tap 128, 64 120
PRB_R7 Stereo B Yes 0 No 64 88
PRB_R8 Stereo B Yes 3 No 64 120
PRB_R9 Stereo B Yes 0 20-tap 64 128
PRB_R10 Right B Yes 0 No 64 46
PRB_R11 Right B Yes 3 No 64 60
PRB_R12 Right B Yes 0 20-tap 64 64
PRB_R13 Right C Yes 0 No 32 70
PRB_R14 Stereo C Yes 5 No 32 124
PRB_R15 Stereo C Yes 0 25-tap 32 120
PRB_R16 Right C Yes 0 No 32 36
PRB_R17 Right C Yes 5 No 32 64
PRB_R18 Right C Yes 0 25-tap 32 62
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