Datasheet

Convention:
PageNumber:RegisterNumber:{RegisterBit}[RegisterName](ResetValue)
MCLK
BCLK
PLL
x(RxJ.D)/P
P0:0x04(4)[Clock-GenMuxing ](0h)
MCLK BCLK
50 MHz
MAX
13 MHz
MAX
PLL_CLKIN
50 MHz
MAX
PLL_CLK
110 MHz
MAX
÷NADC
÷MADC
÷AOSR
ADC_CLK ADC_MOD_CLK
÷N
BDIV_CLKIN
26 MHz
MAX
P0:0x1E(30)
[BDIVN _VAL ](1h)
BCLK
N = 1, 2, …, 127, 128
NADC = 1, 2, …, 127, 128
MADC = 1, 2, …, 127, 128
AOSR =1, 2, …, 255, 256
P0:0x12(18)
[ADCNADC _VAL ](1h)
P0:0x13(19)
[ADCMADC_VAL](1h)
P0:0x14(20)
[ADC AOSR _VAL ](80h)
ADC_CLK
33 MHz
MAX
ADC_MOD_CLK
6.5 MHz
MAX
ADC_FS
100 kHz
MAX
P0:0x19(25)[CLKOUTMUX ](0h)
MCLK BCLK PLL_CLK
CDIV_CLKIN
110 MHz
MAX
÷M
M = 1, 2, …, 127, 128
P0:0x1A(26)
[CLKOUTM_VAL ](1h)
CLKOUT (DOUT,GPIO1,GPIO2)
ADC_CLK ADC_MOD_CLK
Note:
MADCx AOSR >
IADC
WhereIADCnumberofinstructions(InstructionCount)forthe ADCMACengine,itisprogrammablefrom2,4, …,510.
P0:0x05(5)[PLL P andR -VAL ](11h)
P0:0x06(6)[PLL J -VAL ](4h)
P0:0x07(7)[PLL D-VAL MSB ](0h)
P0:0x08(8)[PLL D-VAL LSB ](0h)
BCLKisanoutputinmastermode .
P0:0x1B(27):3[ADCInterfaceControl 1]
13 MHz
MAX
50 MHz
MAX
PLL_CLK_INREG
CODEC_CLKINREG
BCLKisaninputinslavemode
P0:0x1B(27):3 [ADCInterfaceControl ](0h)
13 MHz
MAX
50 MHz
MAX
ADC_CLKIN
P0:0x35(53)
[DOUTControl ](1Eh)
P0:0x04(4)[Clock-GenMuxing ](0h)
P0:0x1D(29)
[ADCInterfaceControl 2]
(2h)
TLV320ADC3101
SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ...................................................................................................................................... www.ti.com
A detailed diagram of the audio clock section of the TLV320ADC3101 is shown in Figure 31 .
Figure 31. Audio Clock Generation Processing
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