Datasheet

RD(n) RD(n+1)
2 1
0
3 03
2 1
3
LD(n)
RIGHT CHANNEL LEFT CHANNEL
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3 n-1 n-2 n-3 n-1 n-2 n-3
Ch_Offset_1 = 0 Ch_Offset_2 = 3
RD(n) RD(n+1)
2 1
0
3 03
2 1
3
LD(n)
RIGHT CHANNEL LEFT CHANNEL
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3 n-1 n-2 n-3 n-1 n-2 n-3
Ch_Offset_1 = 0 Ch_Offset_2 = 3
TLV320ADC3101
www.ti.com ...................................................................................................................................... SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009
Figure 29. DSP Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 3
Figure 30 shows the timing diagram for the DSP mode with left and right channels swapped, Ch_Offset_1 = 0,
and Ch_Offset_2 = 3. The MSB of the right channel is valid on the first falling edge of the bit clock after the rising
edge of the word clock. And, the MSB of the left channel is valid three bit-clock cycles after the LSB of right
channel, because the offset for the left channel is 3.
Figure 30. DSP Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 3, Channel Swap
Enabled
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