Datasheet

LD(n) LD(n+1)
2 1
0
3 03
2 1
3
RD(n)
LEFTCHANNEL RIGHTCHANNEL
LD(n)=n'thsampleofleftchanneldate RD(n)=n'thsampleofrightchanneldate
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3 n-1 n-2 n-3 n-1 n-2 n-3
LD(n)
LD(n+1)
2 1
0
3 03
2 1
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel DatA RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2
n-3
n-1 n-2
n-3
n-1 n-2
n-3
Ch_Offset_1 = 1
LD(n) LD (n+1)
2 1
0
3 03
2 1
3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2
n-3
n-1 n-2
n-3
n-1 n-2
n-3
Ch_Offset_1 = 0
TLV320ADC3101
SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ...................................................................................................................................... www.ti.com
Figure 26. DSP Mode (Standard Timing)
Figure 27 shows the DSP mode timing with Ch_Offset_1 = 1.
Figure 27. DSP Mode With Ch_Offset_1 = 1
Figure 28 shows the DSP mode timing with Ch_Offset_1 = 0 and bit clock inverted.
Figure 28. DSP Mode With Ch_Offset_1 = 0, Bit Clock Inverted
For DSP mode, the number of bit clocks per frame should be greater than twice the programmed word length of
the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least
the programmed word length of the data.
Figure 29 shows the DSP time-slot-based mode without channel swapping, and with Ch_Offset_1 = 0 and
Ch_Offset_2 = 3. The MSB of left channel data is valid on the first falling edge of the bit clock after the rising
edge of the word clock. Because the right channel has an offset of 3, the MSB of its data is valid on the third
falling edge of the bit clock after the LSB of the left-channel data. As in the case of other modes, the serial output
bus is put in the high-impedance state, if 3-stating of the output is enabled, during all the extra bit-clock cycles in
the frame.
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