Datasheet

WCLK
BCLK
DOUT
t (BCLK)
H
t (WS)
h
t (BCLK)
L
t (WS)
s
t (WS)
h
t (DO-BCLK)
d
t (WS)
h
t
f
t
r
(see NOTE)
TYPICAL CHARACTERISTICS
-140
-120
-100
-80
-60
-40
-20
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Frequency-kHz
dB
TLV320ADC3101
SLAS553A – NOVEMBER 2008 – REVISED SEPTEMBER 2009 ...................................................................................................................................... www.ti.com
All specifications at 25 ° C, DVDD = 1.8 V
Note A. Falling edge inside a frame for WCLK is arbitrary inside frame.
IOVDD = 1.8 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
H
(BCLK) BCLK high period 35 35 ns
t
L
(BCLK) BCLK low period 35 35 ns
t
s
(WS) BCLK/WCLK setup time 10 8 ns
t
h
(WS) BCLK/WCLK hold time 10 8 ns
t
d
(DO-BCLK) BCLK to DOUT delay time 25 20 ns
t
r
Rise time 15 8 ns
t
f
Fall time 15 8 ns
NOTE: All timing specifications are measured at characterization.
Figure 5. DSP Timing in Slave Mode
Figure 6. Line Input to ADC FFT Plot
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