Datasheet

TLV320ADC3001
www.ti.com SLAS548C –OCTOBER 2008– REVISED APRIL 2011
Page 1 / Register 53: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not write to this register.
Page 1 / Register 54: Left ADC Input Selection for Left PGA
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved. Do not write any value other than reset value.
D6 R/W 0 Left ADC Common-Mode Select
0: Left ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage.
1: Left ADC channel unselected inputs are biased weakly to the ADC common-mode voltage.
D5–D4 R/W 11 Differential Pair [Plus = IN1L(P) and Minus = IN1R(M)]
00: 0-dB setting is chosen.
01: –6-dB setting is chosen.
10–11: Not connected to the left ADC PGA
D3–D2 R/W 11 Reserved. Do not write any value other than reset value.
D1–D0 R/W 11 IN1R(M) Pin (Single-Ended)
(1)
00: 0 dB setting is chosen.
01: –6 dB setting is chosen.
10–11: Not connected to the left ADC PGA.
(1) To maintain the same PGA output level for both single-ended and differential pairs, the single-ended inputs have a 2× gain applied.
Page 1 / Register 55: Right ADC Input selection for Right PGA
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D2 R/W 11 Reserved. Do not write any value other than reset value.
D1–D0 R/W 11 IN1R(M) Pin (Single-Ended)
(1)
00: 0-dB setting is chosen.
01: –6-dB setting is chosen.
10–11: Not connected to the right ADC PGA.
(1) To maintain the same PGA output level for both single-ended and differential pairs, the single-ended inputs have a 2× gain applied.
Page 1 / Register 56: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not write to this register.
Page 1 / Register 57: Right ADC Input Selection for Right PGA
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 Reserved. Do not write any value other than reset value.
D6 R/W 0 Right ADC Common-Mode Select
0: Right ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage.
1: Right ADC channel unselected inputs are biased weakly to the ADC common-mode voltage.
D5–D4 R/W 11 Differential Pair [Plus = IN1L(P) and Minus = IN1R(M)]
00: 0-dB setting is chosen.
01: –6 dB setting is chosen.
10–11: Not connected to the right ADC PGA
D3–D2 R/W 11 Reserved. Do not write any value other than reset value.
D1–D0 R/W 11 IN1L(P) Pin (Single-Ended)
(1)
00: 0-dB setting is chosen.
01: –6-dB setting is chosen.
10–11: Not connected to the right ADC PGA
(1) To maintain the same PGA output level for both single-ended and differential pairs, the single-ended inputs have a 2× gain applied.
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