Datasheet

TLV320ADC3001
SLAS548C –OCTOBER 2008– REVISED APRIL 2011 www.ti.com
Page 1 / Register 26: Dither Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 DC Offset Into Input of Left ADC; Signed Magnitude Number in ±15-mV Steps
1111: –105 mV
...
1011: –45 mV
1010: –30 mV
1001: –15 mV
0000: 0 mV
0001: 15 mV
0010: 30 mV
0011: 45 mV
...
0111: 105 mV
D3–D0 R/W 0000 DC Offset Into Input of Right ADC; Signed Magnitude Number in ±15-mV Steps
1111: –105 mV
...
1011: –45 mV
1010: –30 mV
1001: –15 mV
0000: 0 mV
0001: 15 mV
0010: 30 mV
0011: 45 mV
...
0111: 105 mV
Page 1 / Register 27 Through Page 1 / Register 50: Reserved
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not write to these registers.
Page 1 / Register 51: MICBIAS Control
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D5 R 000 Reserved. Do not write any value other than reset value.
D4–D3 R/W 00 00: MICBIAS2 is powered down.
01: MICBIAS2 is powered to 2 V.
10: MICBIAS2 is powered to 2.5 V.
11: MICBIAS2 is connected to AVDD.
D2–D0 R 000 Reserved. Do not write any value other than reset value.
Page 1 / Register 52: Left ADC Input Selection for Left PGA
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R/W 1111 Reserved. Do not write any value other than reset value.
D3–D2 R/W 11 IN2L Pin (Single-Ended)
(1)
00: 0-dB setting is chosen.
01: –6-dB setting is chosen.
10: Is not connected to the left ADC PGA
11: Is not connected to the left ADC PGA
D1–D0 R/W 11 IN1l(P) Pin (Single-Ended)
(1)
00: 0-dB setting is chosen.
01: –6-dB setting is chosen.
10: Is not connected to the left ADC PGA
11: Is not connected to the left ADC PGA
(1) To maintain the same PGA output level for both single-ended and differential pairs, the single-ended inputs have a 2× gain applied.
62 Copyright © 2008–2011, Texas Instruments Incorporated