Datasheet

TLV320ADC3001
SLAS548C –OCTOBER 2008– REVISED APRIL 2011 www.ti.com
Page 0 / Register 42: Interrupt Sticky Flags (Overflow)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R 0000 Reserved
D3
(1)
R 0 Left ADC Overflow Flag
0: No overflow in left ADC
1: Overflow has occurred in left ADC since last read of this register.
D2
(1)
R 0 Right ADC Overflow Flag
0: No overflow in right ADC
1: Overflow has occurred in right ADC since last read of this register.
D1
(1)
R 0 ADC Barrel-Shifter Output-Overflow Flag
0: No overflow in ADC barrel-shifter output
1: Overflow has occurred in ADC barrel-shifter output since last read of this register.
D0 R 0 Reserved
(1) Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
Page 0 / Register 43: Interrupt Flags (Overflow)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R 0000 Reserved
D3 R 0 Left ADC Overflow Flag
0: No overflow in left ADC
1: Overflow has occurred in left ADC.
D2 R 0 Right ADC Overflow Flag
0: No overflow in right ADC
1: Overflow has occurred in right ADC.
D1 R 0 ADC Barrel-Shifter Output-Overflow Flag
0: No overflow in ADC barrel-shifter output
1: Overflow in ADC barrel-shifter output
D0 R 0 Reserved
Page 0 / Register 44: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not write to this register.
Page 0 / Register 45: Interrupt Flags—ADC
READ/ RESET
BIT DESCRIPTION
(1)
WRITE VALUE
D7 R 0 Reserved
D6 R 0 Left AGC Noise Threshold Flag:
0: Left ADC signal power ≥ noise threshold for left AGC
1: Left ADC signal power < noise threshold for left AGC
D5 R 0 Right AGC Noise Threshold Flag:
0: Right ADC signal power ≥ noise threshold for right AGC
1: Right ADC signal power < noise threshold for right AGC
D4 R 0 ADC miniDSP engine standard interrupt-port output
D3 R 0 ADC miniDSP engine auxilliary interrupt-port output
D2–D0 R 000 Reserved
(1) Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
Page 0 / Register 46: Reserved
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not write to this register.
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