Datasheet

TLV320ADC3001
www.ti.com
SLAS548C OCTOBER 2008 REVISED APRIL 2011
Page 0 / Register 35: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7D0 R XXXX XXXX Reserved. Do not write to this register.
Page 0 / Register 36: ADC Flag Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R 0 0: Left ADC PGA, applied gain programmed gain
1: Left ADC PGA, applied gain = programmed gain
D6 R 0 0: Left ADC powered down
1: Left ADC powered up
D5
(1)
R 0 0: Left AGC not saturated
1: Left AGC applied gain = maximum applicable gain by left AGC
D4 R 0 Reserved. Do not write any value other than reset value.
D3 R 0 0: Right ADC PGA, applied gain programmed gain
1: Right ADC PGA, applied gain = programmed gain
D2 R 0 0: Right ADC powered down
1: Right ADC powered up
D1
(1)
R 0 0: Right AGC not saturated
1: Right AGC applied gain = maximum applicable gain by right AGC
D0 R 0 Reserved. Do not write any value other than reset value.
(1) Sticky flag bits. These are read-only bits. They are automatically cleared once they are read and are set only if the source trigger occurs
again.
Page 0 / Register 37: Data Slot Offset Programmability 2 (Ch_Offset_2)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7D0 R/W 0000 0000 0000 0000: Offset = 0 BCLKs. Offset is measured with respect to the end of the first channel
(1)
0000 0001: Offset = 1 BCLK
0000 0010: Offset = 2 BCLKs
...
1111 1110: Offset = 254 BCLKs
1111 1111: Offset = 255 BCLKs
(1) Usage controlled by page 0 / register 38, bit D0, time_slot_mode enable
Page 0 / Register 38: I
2
S TDM Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7D5 R 000 Reserved. Do not write any value other than reset value.
D4 R/W 0 0: Channel swap disabled
1: Channel swap enabled
D3D2 R/W 00 00: Both left and right channels enabled
01: Left channel enabled
10: Right channel enabled
11: Both left and right channels disabled
D1 R/W 1 0: early_3-state disabled
1: early_3-state enabled
D0 R/W 0 0: time_slot_mode disabled both channel offsets controlled by Ch_Offset_1 (page 0 / register 28)
1: time_slot_mode enabled channel-1 offset controlled by Ch_Offset_1 (page 0 / register 28) and
channel-2 offset controlled by Ch_Offset_2 (page 0 / register 37)
Page 0 / Register 39 Through Page 0 / Register 41: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7D0 R XXXX XXXX Reserved. Do not write to these registers.
Copyright © 20082011, Texas Instruments Incorporated 51